Multilayer interlevel dielectrics using phosphorus-doped glass

Details Multilayer interlevel dielectrics using phosphorus-doped glass Multilayer interlevel dielectrics using phosphorus-doped glass

1996-06-10

1998-10-06

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438626, 438697, 438699, 438784, 438782, 438624, 438631, 438622, H01L 2144

Patent

active

058175717

ABSTRACT:
A method for forming a planarized interlevel dielectric layer without degradation due to microloading effect is described. A first conformal layer of silicon dioxide is deposited overlying a conducting layer over an insulating layer on a semiconductor substrate. A second silicon dioxide layer is deposited overlying the first conformal silicon dioxide layer. A doped glass layer is deposited overlying the second silicon dioxide layer. The doped glass layer is coated with a spin-on-glass layer. The spin-on-glass layer is etched back until the interlevel dielectric layer is planarized. The microloading effects from the etching back of the spin-on-glass layer of the interlevel dielectric layer are lower than microloading effects in a conventional interlevel dielectric layer.

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