Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-18
2004-05-04
Vu, Hung (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S336000, C257S344000
Reexamination Certificate
active
06730976
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a gate electrode of a MOS transistor or the like and a method of manufacturing the gate electrode.
2. Description of Related Art
As a material for a gate electrode of a MOS transistor, polycrystalline silicon has been generally used. However, when the gate electrode is used as a mask to implanted ions in order to produce an impurity-diffused layer, it has a problem in that the implanted ions penetrate through the gate electrode, i.e., a grain boundary in the polycrystalline silicon, and arrive at. a channel region of the transistor, thereby impairing the desired characteristics of the transistor.
Various methods have been proposed to solve the above problem.
FIG. 9
is a cross-sectional view showing the structure of a MOS transistor described, e.g., in Japanese Patent Application Laid-open No. 2-298074. In the drawing, reference numeral
1
designates a semiconductor substrate;
2
designates a gate oxide film;
3
designates a first polycrystalline silicon or polysilicon film;
4
designates a second polycrystalline silicon film;
5
designates a gate electrode;
6
designates a source region;
7
designates a drain region; and
8
designates a channel region.
As shown in
FIG. 9
, the gate electrode
5
of the MOS transistor has a multilayer film structure comprising the first polycrystalline silicon film
3
and the second polycrystalline silicon film
4
, which differ from each other in the size of their crystal grains diameter. Consequently, even when ions are implanted to the semiconductor substrate in order to produce source/drain regions
6
and
7
while the gate electrode
5
is used as a mask, from the view point of the implanted ions the multilayer structure causes the grain-boundary density of the gate electrode to appear to increase. Consequently, penetration of the ions through the grain boundary within the gate electrode is retarded, thereby preventing the ions from arriving at the channel region
8
.
In such a structure of the conventional gate electrode, the thickness of each layer of the multilayer structure, particularly, the thickness and crystal grain diameter of the first polycrystalline silicon film
3
serving as a lower film, is not controlled accurately. Accordingly, for example, in a case where ions are implanted at a large angle in relation to the surface of the substrate to form a shallow impurity diffused layer in a gate overlap LDD structure while the gate electrode is used as a mask, as shown in
FIG. 10
, there exist ions
9
a
which are directly implanted to the sidewall of the first polycrystalline silicon film
3
. The ions have a chance of penetrating through the grain boundary in the polycrystalline silicon film
3
and arriving at the channel region. The ions that arrived at the channel region form an impurity
10
in the channel region. When the potential of the gate electrode is turned off, the impurity
10
acts as a path for an electric current flowing from the source region to the drain region, thereby causing an off leakage current. The off leakage current results in, for example, deletion of the information stored in memory cells or an increase in power consumption, and it considerably impairs the characteristic of the transistor.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the problem set forth, and a first object of the present invention is to produce a semiconductor device having a gate electrode of multilayer structure which prevents penetration of ions (hereinafter referred to as “tilted ions”) traveling through a grain boundary to a channel region even at the time of the tilted ion implantation at a large angle with respect to the substrate.
A second object of the present invention is to provide a semiconductor device having a gate electrode of multilayer structure which prevents penetration of tilted ions through a grain boundary to a channel region as a result of tilted ion implantation and which has a lower resistance.
A third object of the present invention is to provide a method of manufacturing a semiconductor device having a multilayer structure which prevents penetration of tilted ions through a grain boundary to a channel region even at the time of tilted ion implantation at a large angle.
A fourth object of the present invention is to provide a method of manufacturing a semiconductor device having a gate electrode of multilayer structure which prevents penetration of tilted ions through a grain boundary to a channel region as a result of tilted ion implantation and which has a lower resistance.
According to a first aspect of the present invention, there is provided a semiconductor device having a gate electrode of multilayer structure comprising a semiconductor substrate; a gate electrode made of multilayer film formed on the surface of the semiconductor substrate by way of a gate insulating film; and a pair of impurity diffused layers which are formed on the surface of the semiconductor substrate by means of tilted ion implantation while the gate electrode is used as a mask, wherein the thickness of the lowest film of the multilayer film is greater than the range of ions in a thicknesswise direction in the lowest film when the ions are implanted to sidewalls of the multilayer film by means of the tilted ion implantation.
In the semiconductor device, the gate electrode may have a two-layer film structure comprising a lower film formed from an amorphous silicon film and an upper film formed from a polycrystalline silicon film.
In the semiconductor device, the gate electrode may have a two-layer film structure comprising a lower film and an upper film, and the upper film comprises a first upper film and a second upper film provided so as to surround the sidewalls of the first upper film.
According to a second aspect of the present invention, a method of manufacturing a semiconductor device having a gate electrode of multilayer structure comprising the steps of forming a gate electrode from a multilayer film on the surface of a semiconductor substrate by way of a gate insulting film; forming a pair of impurity diffused layers on the semiconductor substrate by tilted ion implantation while the gate electrode is used as a mask; and forming the lowest film of the multilayer film in such a way that a thickness of the lowest film is greater than the range of ions in a thicknesswise direction in the lowest film when the ions are implanted to the sidewalls of the lowest film by means of the tilted ion implantation.
In the method of manufacturing a semiconductor device having a gate electrode of multilayer structure, the step of forming a gate electrode may comprise the steps of forming a lower film from an amorphous silicon film on the semiconductor substrate and forming an upper film from a polycrystalline silicon film on the lower film.
In the method of manufacturing a semiconductor device having a gate electrode of multilayer structure, wherein the lower film formed from an amorphous silicon film may be formed by ion implantation of oxygen or silicon to the polycrystalline silicon film.
The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5276347 (1994-01-01), Wei et al.
patent: 5355006 (1994-10-01), Iguchi
patent: 5773347 (1998-06-01), Kimura et al.
patent: 1-14968 (1989-01-01), None
patent: 2-292833 (1990-12-01), None
patent: 2-298074 (1990-12-01), None
patent: 3-3365 (1991-01-01), None
patent: 3-218639 (1991-09-01), None
patent: 4-11633 (1992-04-01), None
patent: 5-267655 (1993-10-01), None
Harada Akihiko
Igarashi Motoshige
McDermott & Will & Emery
Renesas Technology Corp.
Vu Hung
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