Multilayer ferroelectric capacitor structure

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Reexamination Certificate

active

06172385

ABSTRACT:

DESCRIPTION
1. Field of the Invention
The present invention relates to ferroelectric films and in particular to semiconductor structures which contain a multilayer ferroelectric film as a capacitive element. The present invention also describes a method which can be employed in fabricating multilayer ferroelectric films that exhibit reduced leakage current and improved microstructural porosity.
2. Background of the Invention
Layered ferroelectric films such as strontium bismuth tantalate (SBT), strontium bismuth niobate (SBN) and strontium bismuth tantalate niobate (SBTN) generally require long annealing times (on the order of 30-90 minutes or longer) and high processing temperatures (800° C.) for optimum film crystallization and electrical properties. The resultant ferroelectric films are characterized as having highly asymmetric grains and an inherent porosity.
If lower processing temperatures or times are employed, the resultant ferroelectric films typically exhibit poor leakage behavior, low remanent polarization and low fatigue. In addition, under prior art annealing conditions, oxidation of the electrodes and the underlying contacts may result in high resistivity contacts.
Moreover, by utilizing prior art annealing conditions, interfacial layers may result between the electrodes and underlying contact and/or between the ferroelectric material and the electrode. For instance, Bi readily forms Bi/Pt alloys which may degrade the performance of the capacitor.
In the semiconductor industry, single layered ferroelectric films comprising one ferroelectric material or composition are generally employed in fabricating various electronic devices such as non-volatile storage devices (non-volatile random access memory (NVRAM) and ferroelectric random access memory (FRAM)). The prior art semiconductor devices containing a single layer ferroelectric film have limited operations since the single layered films are inherently porous and leaky. These properties can result in device failures; therefore a solution to the same is required.
In view of the above drawbacks with prior art methods of producing single layer ferroelectric films, there is a continued need for developing new and improved methods of fabricating ferroelectric films which, when used as a capacitive element of a semiconductor device, exhibit reduced leakage current, as well as having improved microstructural porosity, polarization and fatigue. It is noted that the term “single layered ferroelectric film” is used herein to denote a film composed of one “multilayer ferroelectric film” is used herein to denote a film composed of more than one ferroelectric material and/or more than one composition of the ferroelectric material.
SUMMARY OF THE INVENTION
The present invention provides a multilayer ferroelectric capacitor structure and a method for fabricating a multilayer ferroelectric film which exhibits reduced leakage current and improved microstructural porosity than heretofore reported in prior art single layer ferroelectric films.
In one aspect of the present invention, the multilayer ferroelectric film of the present invention is used in fabricating a capacitive element. Specifically, the present invention provides a capacitive element which comprises a substrate; a first electrode formed on said substrate; a multilayer ferroelectric film formed on said first electrode, said multilayer ferroelectric film being composed of (i) more than one ferroelectric material, (ii) more than one composition of the ferroelectric material or (iii) both (i) and (ii); and a second electrode formed on the multilayer ferroelectric film.
The term “ferroelectric material or composition” is used herein to denote any crystalline, polycrystalline, or amorphous substance which displays spontaneous electric polarization. The preferred ferroelectric materials or compositions that are employed in the present invention are perovskite-type oxides which contain at least one acidic oxide containing a metal from Group IVB (Ti, Zr or Hf), VB (V, Nb or Ta), VIB (Cr, Mo or W), VIIB (Mn or Re) or IB (Cu, Ag or Au) of the Periodic Table of Elements (CAS version) and at least one additional cation having a positive formal charge of from about 1 to about 3.
Suitable perovskite-type oxides include, but are not limited to: titanate-based ferroelectrics, manganatebased materials, cuprate-based materials, tungsten bronze-type niobates, tantalates, or titanates, and bismuth layered-tantalates, niobates or titanates. Of these perovskite-type oxides, strontium bismuth tantalate, strontium bismuth niobate, bismuth titanate, strontium bismuth tantalate niobate, lead zirconate titanate and lead lanthanum zirconate titanate are highly preferred in the present invention.
The term “substrate” is used broadly to denote any semiconducting wafer or material which may contain active device regions embedded therein as well as an insulator layer on its upper surface.
The present invention also provides non-volatile storage devices such as NVRAM and FRAM which comprise at least the multilayer ferroelectric film, i.e. capacitive element, of the present invention. The multilayer ferroelectric film of the present invention can also be employed as the capacitive element in dynamic random access memory (DRAM) cells.
Another aspect of the present invention relates to a method of fabricating a multilayer ferroelectric film which exhibits reduced leakage current and improved microstructural porosity. In accordance with this aspect of the present invention, the method comprises the steps of:
(a) forming a multilayer ferroelectric film, said multilayer ferroelectric film being composed of more than one ferroelectric material and/or more than one composition of the ferroelectric material; and
(b) annealing said multilayer ferroelectric film at a temperature below 800° C. for a time period of from about 5 to about 120 minutes.


REFERENCES:
patent: 5558946 (1996-09-01), Nishimoto
patent: 5645885 (1997-07-01), Nishimoto
patent: 6094369 (2000-07-01), Ozawa et al.

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