Multilayer electrical interconnect fabrication with few process

Details Multilayer electrical interconnect fabrication with few process Multilayer electrical interconnect fabrication with few process

1991-05-28

1992-06-02

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156645, 156652, 156655, 156656, 1566591, 156668, 156902, B44C 122, C23F 100, B29C 3700

Patent

active

051183854

ABSTRACT:
Method for making a multilayer electrical interconnect with stacked pillars between layers using a minimal number of conventional process steps. The method includes sputtering a chromium/copper/titanium trilayer on a dielectric base, depositing a patterned mask on the trilayer, etching the exposed trilayer, removing the mask, depositing a layer of polyimide over the unetched copper, forming a via in the polyimide above the copper, electrolessly plating nickel into the via, and polishing the interconnect to form a planar top surface.

REFERENCES:
patent: 4670091 (1987-06-01), Thomas et al.
patent: 4702792 (1987-10-01), Chow et al.
patent: 4810332 (1989-03-01), Pan
patent: 4983250 (1991-01-01), Pan
patent: 5011580 (1991-04-01), Pan et al.
patent: 5071518 (1991-12-01), Pan
patent: 5082718 (1992-01-01), Chantraine et al.
Tessier et al, "Process Condiserations in Fabricating Thin Film Multichip Modules," International Electronics Packaging Society Conference Proceedings, 1989, pp. 294-313.
Endo et al, "Material and Pressing Technologies of Polyimide for Advanced Electronic Devices," Journal of the Electrochemical Society, vol. 134, No. 10 (Oct. 1987), pp. 2522-2527.

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