Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
1999-10-28
2002-08-06
Baxter, Janet (Department: 1752)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S314000, C430S316000, C430S330000
Reexamination Certificate
active
06428942
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
Embodiments of the invention relate to methods for forming multilayer circuit structures.
BACKGROUND OF THE INVENTION
Multilayer circuit structures can be used to electrically communicate two or more electrical devices such as two or more computer chips. Multilayer circuit structures typically contain multiple conductive layers separated by one or more dielectric layers. Via structures disposed in apertures in the dielectric layers provide conductive paths so that electrical signals can pass from one conductive layer to another conductive layer. Multiple via structures in successive dielectric layers can be used to form a conductive path from an inner region to an outer region of a multilayer circuit structure.
The via structures in successive dielectric layers can be staggered in a multilayer circuit structure. For example, as shown in
FIG. 1
, a plurality of staggered via structures
11
are in electrical communication with each other. The staggered conductive path formed by the via structures
11
can provide communication between a core structure
12
and an outer surface of the multilayer circuit structure
10
. Each of the via structures
11
shown in
FIG. 1
is in the form of a conductive coating on an aperture wall in a dielectric layer. Unfortunately, staggering the via structures can consume valuable area in a multilayer circuit structure and can increase the signal run length. This can decrease the density of the circuitry in a multilayer circuit structure. Moreover, the metal coating of via structures of the type shown in
FIG. 1
is thin. Open circuits can form if the coating is not thick enough or is not uniform.
It would be desirable to provide a method for efficiently producing a reliable high-density multilayer circuit structure in a cost effective manner.
SUMMARY OF THE INVENTION
Embodiments of the invention are directed to methods for forming multilayer circuit structures, particularly high density multilayer circuit structures, having stacked via structures. The via structures are preferably stacked conductive posts.
One embodiment of the invention can be directed to a method for forming a multilayer circuit structure. The method comprises: forming a first plurality of conductive posts on first and second sides of a circuitized core structure, each conductive post having an end proximate to the core structure and an end distal to the core structure; depositing a first dielectric layer on the first side of the core structure; depositing a second dielectric layer on the second side of the core structure; removing dielectric layer material from the distal ends of the first plurality of conductive posts; and forming a second plurality of conductive posts on the distal ends of the first plurality of conductive posts.
Another embodiment is directed a method comprising: forming a first plurality of conductive posts on a side of a circuitized core structure, each conductive post having an end proximate to the core structure and an end distal to the core structure; laminating a dielectric layer on the core structure; depositing a protective layer on the dielectric layer; removing dielectric layer material from the distal ends of the first plurality of conductive posts through the protective layer; and forming a second plurality of conductive posts on the distal ends of the first plurality of conductive posts.
These and other embodiments of the invention can be described with reference to the Figures and the Detailed Description.
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Pan et al., “A Planar Approach to High Density Copper-Polymide Interconnect Fabrication,” pp. 174-189, Proceeding of the Technical Conference —8thInt'l Electronics Packaging Conference (1988).
Iwasaki et al., “A Pillar-Shaped Via Structure in a Cu-Polymide Multilayer Substrate,” pp. 127-131, Proceedings of the 1989 Japan International Electronic Manufacturing Technology Symposium.
Jiang Hunt Hang
Lee Michael Guang-Tzong
McCormack Mark
Takahashi Yasuhito
Wang Wen-chou Vincent
Baxter Janet
Coudert Brothers LLP
Fujitsu Limited
Walke Amanda C.
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