Multicore memory management system

Details Multicore memory management system Multicore memory management system

2006-08-21

2010-06-01

Nguyen, Hiep T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

07730261

ABSTRACT:
A multiprocessing system includes, in part, a multitude of processing units each in direct communication with a bus, a multitude of memory units in direct communication with the bus, and at least one shared memory not in direct communication with the bus but directly accessible to the plurality of processing units. The shared memory may be a cache memory that stores instructions and/or data. The shared memory includes a multitude of banks, a first subset of which may store data and a second subset of which may store instructions. A conflict detection block resolves access conflicts to each of the of the banks in accordance with a number of address bits and a predefined arbitration scheme. The conflict detection block provides each of the processing units with sequential access to the banks during consecutive cycles of a clock signal.

REFERENCES:
patent: 4445174 (1984-04-01), Fletcher
patent: 5586270 (1996-12-01), Rotier et al.
patent: 6523090 (2003-02-01), Tremblay
patent: 6725336 (2004-04-01), Cherabuddi
patent: 6976131 (2005-12-01), Pentkovski et al.
patent: 2005/0204112 (2005-09-01), O'Connor et al.
patent: 2006/0004963 (2006-01-01), Mattina et al.

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