Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2005-05-17
2005-05-17
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S147000, C711S150000, C711S168000, C712S035000, C709S213000
Reexamination Certificate
active
06895479
ABSTRACT:
A multi-core digital signal processor is disclosed having a shared program memory with conditional write protection. In one embodiment, the digital signal processor includes a shared program memory, an emulation logic module, and multiple processor cores each coupled to the shared program memory by corresponding instruction buses. The emulation logic module preferably determines the operating modes of each of the processors, e.g., whether they are operating in a normal mode or an emulation mode. In the emulation mode, the emulation logic can alter the states of various processor hardware and the contents of various registers and memory. The instruction buses each include a read/write signal that, while their corresponding processor cores are in normal mode, is maintained in a read state. On the other hand, when the processor cores are in the emulation mode, the processor cores are allowed to determine the state of the instruction bus read/write signals. Each instruction bus read/write signal is preferably generated by a logic gate that prevents the processor core from affecting the read/write signal value in normal mode, but allows the processor core to determine the read/write signal value in emulation mode. In this manner, the logic gate prevents write operations to the shared program memory when the emulation logic de-asserts a signal indicative of emulation mode, and allows write operations to the shared program memory when the emulation logic asserts the signal indicative of emulation mode. The logic gate is preferably included in a bus interface module in each processor core.
REFERENCES:
patent: 5872993 (1999-02-01), Brown
patent: 6253293 (2001-06-01), Rao et al.
patent: 6327648 (2001-12-01), Hedayat et al.
patent: 6430664 (2002-08-01), Chauvel et al.
patent: 6526462 (2003-02-01), Elabd
patent: 6564179 (2003-05-01), Belhaj
Bui Dan K.
Hopkins Harland Glenn
Luo Yi
McGonagle Kevin A.
Nguyen Tai H.
Brady III W. James
Marshall, Jr. Robert D.
Padmanabhan Mano
Song Jasmine
Telecky , Jr. Frederick J.
LandOfFree
Multicore DSP device having shared program memory with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multicore DSP device having shared program memory with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multicore DSP device having shared program memory with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3379081