Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2000-07-28
2002-03-19
Gaffin, Jeffrey (Department: 2841)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S723000, C257S784000, C257S786000, C361S783000
Reexamination Certificate
active
06359340
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a multichip module (MCM), and more specifically to a multichip module having a stacked chip arrangement.
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the packages for protecting and interconnecting IC chips have the same trend, too.
With ever increasing demands for miniaturization and higher operating speeds, multichip modules (MCMs) are increasingly attractive in a variety of electronics. MCMs which contain more than one die can help minimize the system operational speed restrictions imposed by long printed circuit board connection traces by combining, for example, the processor, memory, and associated logic into a single package. In addition, MCMs decrease the interconnection length between IC chips thereby reducing signal delays and access times.
The most common MCM is the “side-by-side” MCM. In this version two or more IC chips are mounted next to each other (or side by side each other) on the principal mounting surface of a common substrate. Interconnections among the chips and conductive traces on the substrate are commonly made via wire bonding. The side-by-side MCM, however, suffers from a disadvantage that the package efficiency is very low since the area of the common substrate increases with an increase in the number of semiconductor chips mounted thereon.
Therefore, U.S. Pat. No. 5,323,060 teaches a multichip stacked device (see
FIG. 1
) comprising a first semiconductor chip
110
attached to a substrate
120
and a second semiconductor chip
130
stacked atop the first semiconductor chip
110
. The chips
110
,
130
are respectively wire bonded to the substrate
120
. U.S. Pat. No. 5,323,060 is characterized by using an adhesive layer
140
between the two chips
110
,
130
to provide clearance between the chips for the loops of the bonding wires. The wire bonding process of the underlying chip
110
must be completed before the chip
130
can be stacked on the chip
110
. This means that the die bonding process must be repeated for each additional layer of the stack. In addition to adding extra process steps, there is a chance of damaging the underlying wires. Additionally, the clearances between two adjacent chips in the stack are quite tight. This will lead to limited processing window in wire binding process, thereby creating reliability problems of the bonding wires.
Typically, the normal loop height of bonding wires is generally about 10 to 15 mils. As thinner packages have been developed, the loop height has been reduced with conventional bonding techniques down to about 6 mils in height by changes in the loop parameters, profile and wire types. However, this loop height is considered to be a minimum obtainable loop height as the loop height less than 6 mils will cause wire damage and poor wire pull strength. Therefore, using this conventional bonding technique, the adhesive layer
140
must have a thickness of at least 8 mils to prevent the bonding wires
150
from contacting the chip
130
. Typical materials for the adhesive layer
140
include epoxy and tape. However, it is very difficult to form an epoxy layer with a stable bond line thickness above 3 mils. Further, even using a tape with a thickness of 8 mils, it will increase the cost of the final product, and the reliability of resulted package will suffer from the CTE mismatch between the thermoplastic tape and the silicon chip.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide a multichip module which allows two chips in a stack to be attached to the substrate prior to wire bonding.
It is another object of the present invention to provide a multichip module which does not restrict the loop height for the underlying chip, thereby allowing a larger processing window during wire bonding, thereby enhancing the reliability of bonding wires for the underlying chip.
It is a further object of the present invention to provide a multichip module which does not restrict the loop height for the underlying chip, thereby allowing thinner layers of adhesive separating the chips, and reducing the overall height of the assembly.
It is yet a further object of the invention to provide a multichip module comprising a middle chip interposed between an upper chip and a lower chip wherein these three chips are disposed on a substrate in a stacking arrangement. The multichip module of this embodiment is characterized in that the middle chip has a predetermined thickness sufficient to provide clearance between the upper chip and the lower chip for bonding wires of the lower chip thereby preventing the upper chip from damaging the underlying bonding wires.
The multichip module according to a preferred embodiment of the present invention mainly comprises at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bonding pad of the lower chip to permit wire bonding thereof. The wire bonding process of the semiconductor chips are performed after stacking the chips on the substrate. Therefore, the multichip module having a stacked chip arrangement in accordance with the present invention is characterized in that wire bonding of chips can be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.
Further, since no portion of the upper chip interferes with a vertical line of sight of each bonding pad of the lower chip, the upper chip does not restrict the loop height for the lower chip. This provides a larger processing window during wire bonding thereby enhancing the reliability of bonding wires for the underlying chip, and allows thinner layers of adhesive separating the chips thereby reducing the overall height of the assembly.
The multichip module according to another preferred embodiment of the present invention mainly comprises two semiconductor chips mounted to a substrate in a stacking arrangement. The semiconductor chips are characterized by having a plurality of bonding pads along only two mutually perpendicular side edges thereof. Thus, the two chips can be stacked onto the substrate, and then wire-bonded at the same time. Therefore, the wirebonding process of this multichip module can be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost. Further, since no portion of the upper chip interferes with a vertical line of sight of each bonding pad of the lower chip, the upper chip does not restrict the loop height for the lower chip. This provides a larger processing window during wire bonding thereby enhancing the reliability of bonding wires for the underlying chip, and allows thinner layers of adhesive separating the chips thereby reducing the overall height of the assembly.
The multichip module according to still another preferred embodiment of the present invention mainly comprises a middle chip interposed between an upper chip and a lower chip wherein these three chips are disposed on a substrate in a stacking arrangement. These chips also are characterized by having a plurality of bonding pads along only two mutually perpendicular side edges thereof. The multichip module of this embodiment is characterized in that the middle chip has a predetermined thickness sufficient to provide clearance between the upper chip and the lower chip for bonding wires of the lower chip thereby preventing the upper chip from damaging the underlying bonding wires.
REFERENCES:
patent: 5793108 (1998-08-01), Nakanishi et al.
patent: 5998864 (1999-12-01), Khandros et al.
patent: 6051886 (2000-04-01), Fogal et al.
patent: 6252305 (2001-06-01), Lin et al.
Chen Jian Wen
Chen Kuang-Hui
Lin Chun Hung
Tao Su
Wang Shyh-Wei
Advanced Semiconductor Engineering Inc.
Vigushin John B.
LandOfFree
Multichip module having a stacked chip arrangement does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multichip module having a stacked chip arrangement, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multichip module having a stacked chip arrangement will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2843341