Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2000-04-10
2002-10-08
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S723000, C438S107000
Reexamination Certificate
active
06462421
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a multichip module (MCM), and more specifically to a MCM comprising two semiconductor chips respectively wire bonded and flip-chip bonded to opposing surfaces of a substrate.
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the packages for protecting and interconnecting IC chips have the same trend, too.
With ever increasing demands for miniaturization and higher operating speeds, multi-chip modules (MCMs) are increasingly attractive in a variety of electronics. MCMs which contain more than one die can help minimize the system operational speed restrictions imposed by long printed circuit board connection traces by combining, for example, the processor, memory, and associated logic into a single package. In addition, MCMs decrease the interconnection length between IC chips thereby reducing signal delays and access times.
The most common MCM is the “side-by-side” MCM. In this version two or more IC chips are mounted next to each other (or side by side each other) on the principal mounting surface of a common substrate. Interconnections among the chips and conductive traces on the substrate are commonly made via wire bonding. The side-by-side MCM, however, suffers from a disadvantage that the package efficiency is very low since the area of the common substrate increases with an increase in the number of semiconductor chips mounted thereon.
Therefore, the semiconductor industry develops a stacked chip package
100
(see
FIG. 1
) comprising two chips
110
,
130
stacked each other. The chip
110
is attached onto the upper surface of a substrate
150
through an adhesive layer
112
. An adhesive layer
132
is interposed between the chips
110
,
130
. The chips
110
,
130
are respectively connected to wire bondable pads
152
on the upper surface of the substrate
150
through bonding wires
114
,
134
. The lower surface of the substrate
150
is provided with a plurality of solder pads
154
electrically connected to the wire bondable pads
152
on the upper surface of the substrate
150
. Each solder pad
154
is provided with a solder ball
156
for making external electrical connection. A package body
160
encapsulates the chips
110
,
130
, the bonding wires
114
,
134
and a portion of the upper of the substrate
150
. However, the upper chip
130
will interfere wire bonding operation of the lower chip
110
when the upper chip
130
has a size close to the size of the lower chip
110
. Moreover, comparing to the bonding wires
114
for chip
110
, the bonding wires
134
for chip
130
have a much longer wire length and a much higher loop height thereby increasing the difficulty encountered in the wire bonding operation thereof. For example, longer wire with higher loop profile is more prone to break during wire bonding operation and to have problems of wire sweeping during encapsulation. Further, it requires a much thicker package body for stacked chip packages to encapsulate the stacked chips as well as bonding wires having a much longer wire length and a much higher loop height thereby reducing the packaging efficiency.
U.S. Pat. No. 5,973,403 discloses a multichip stacked device (see
FIG. 2
) comprising a wire-bonded semiconductor chip stacked on a flip-chip bonded semiconductor chip. The multichip stacked device comprises a first semiconductor chip
210
attached onto a substrate
220
by flip-chip bonding, and a second semiconductor chip
230
stacked on the first semiconductor chip
210
and wire-bonded to the substrate
220
. The upper surface of the substrate
220
is provided with a plurality of wire bondable pads
222
and a plurality of flip-chip pads
224
. The lower surface of the substrate
220
has a plurality of solder pads
226
. The first semiconductor chip
210
is bonded to the flip-chip pads
224
through a plurality of solder joints. The second semiconductor chip
230
is bonded to the wire bondable pads
222
through a plurality of bonding wires
223
. Since the lower semiconductor chip
210
is electrically connected to the substrate
200
by flip-chip bonding, the upper chip
230
will not become a hindrance to the lower chip
210
.
However, when the chips
210
,
230
are of the same type, address assignment of the bonding pads on the chips
210
,
230
will mirror each other because the semiconductor chip
210
is oriented face down (with its bonding pads (not shown) down with respect to the substrate
220
) for flip-chip bonding. Therefore, address assignment of the wire bondable pads
222
(i.e., address A
1
to D
7
shown in
FIG. 3
) should be a mirror image of that of the flip-chip pads
24
(i.e., address A′
1
to D′
7
shown in FIG.
3
). This makes the circuit layout of the substrate become quite complicated and greatly increases the length and density of the conductive traces (not shown) of the substrate. Further, that will adversely affect the electrical performance of the package, since the impedance, the inductance, and the noise of the conductive traces are in proportion to the length of the conductive traces. High inductance makes package consume more electricity such that integrated circuit and traces inside the chip are more susceptible to power surges. Moreover, similar to the stacked chip package
100
described above, the bonding wires
223
for connecting chip
230
to the wire bondable pads
222
of the substrate
220
have a much longer wire length and a much higher loop height thereby increasing the difficulty encountered in the wire bonding operation thereof. As described above, longer wire with higher loop profile is more prone to break during wire bonding operation and to have problems of wire sweeping during encapsulation. And it requires a much thicker package body for stacked chip packages to encapsulate the stacked chips as well as bonding wires having a much longer wire length and a much higher loop height thereby reducing the packaging efficiency.
U.S. Pat. No. 5,801,072 discloses a multichip module comprising a first semiconductor chip attached onto the upper surface of a substrate by flip-chip bonding, and a second semiconductor chip attached onto the lower surface of the substrate also by flip-chip bonding. However, similar to the multichip stacked device disclosed in U.S. Pat. No. 5,973,403, when the upper and lower chips are of the same type, address assignment of the bonding pads on the upper and lower chips will mirror each other. Because the upper chip is flip-chip bonded to the substrate in a face-down orientation but the lower chip is flip-chip bonded to the substrate in a face-up orientation. This will makes the circuit layout of the substrate become quite complicated and greatly increases the length and density of the conductive traces (not shown) of the substrate. Further, that will adversely affect the electrical performance of the package, since the impedance, the inductance, and the noise of the conductive traces are in proportion to the length of the conductive traces. High inductance makes package consume more electricity such that integrated circuit and traces inside the chip are more susceptible to power surges.
The present invention therefore seeks to provide a multichip module which overcomes, or at least reduces the above-mentioned problems of the prior art.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a multichip module comprising two semiconductor chips of the same type respectively disposed on opposing upper and lower surfaces of a substrate wherein the two chips are respectively wire bonded and flip-chip bonded to the substrate thereby simplifying circuit layout of the substrate and significantly reducing the length of conductive traces formed on the substrate.
It is another object of the present invention to provide a multichip module comprising two semiconductor chips of the same type respectively disposed on opposing upper and lower surfaces of a substrate wherein the two chips are respectively wir
Hsu Kao-Yu
Tao Su
Advanced Semicondcutor Engineering, Inc.
Potter Roy
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