Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
1999-12-17
2002-02-12
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S022000, C710S026000, C710S052000
Reexamination Certificate
active
06347347
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
The invention is related to the field of processors, and in particular to processors utilizing direct memory access (DMA) logic to obtain data from an external entity such as memory associated with another processor.
In processing systems, there is commonly a need to transfer a segment of data from one processing entity to another. For example, in computer systems it is common for a host processor to communicate with input/output (I/O) processors through data structures residing in host memory. One of the processors creates a message for the other processor in host memory, and then notifies the other processor. The other processor then reads the message from host memory. In the case of I/O operations, the message may include data being transferred between the host and an I/O port such as a network interface. In such a case the data may be temporarily buffered in a separate memory forming part of the network interface, and an I/O processor in the network interface is responsible for transferring the data between the I/O port (e.g., network segment) and the host memory. Such systems commonly employ direct memory access (DMA) logic programmed by the interface processor to move the data between the host memory and the interface memory.
In a system like that described, in which an I/O processor (with or without DMA logic) is responsible for moving data between host memory and an external data source/sink such as a network segment, the processor often must examine part of the data in order to take appropriate action with the remainder of the data. An I/O processor in a network interface, for example, may need to examine a header portion of packets being transferred between the host memory and a network segment, to determine if any special action is required with respect to the packets. Such an interface is commonly referred to as a “intelligent” interface, because the I/O processor is capable of performing complex functions in addition to controlling the transfer of data.
In accordance with one known technique, DMA logic is used to transfer a collection of data such as a packet to the interface memory, and then the I/O processor accesses the data as necessary by directly accessing the interface memory. While this approach has the benefit of simplicity, it nonetheless suffers some drawbacks. Accesses by the I/O processor represent demand for the bandwidth resources of the interface memory. Also, the latency of the interface memory may be relatively high from the perspective of the I/O processor, so performance can be negatively affected.
It is also possible to employ two sets of DMA logic, one to transfer data between the host and the interface memory, and another to transfer the data between the interface memory and the I/O processor. This technique also places a load on the bandwidth resources of the interface memory, and requires the I/O processor to carry out the overhead task of controlling the second DMA operation. Both of these have negative performance impacts.
It would be desirable to achieve improved performance in systems having intelligent I/O interfaces, such as intelligent network interface cards.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a technique for transferring data into a memory is disclosed that enables a processor coupled to the memory to enjoy rapid access to selected portions of the data.
In the disclosed data transfer technique, DMA logic transfers data to a memory and simultaneously stores the data into a buffer that is closely coupled to a processor. The processor can access the data from the buffer much more quickly than the data in the memory, so performance is improved. The simultaneous transfer can be selectively enabled and disabled by the processor, so that only those portions of the data that are actually needed by the processor are stored into the buffer. In one embodiment, the technique is part of a processing system on a network interface card (NIC), and is used in conjunction with host memory interface logic during transfers of packets and packet descriptors from host memory to memory on the NIC. The DMA logic is controlled through the use of DMA descriptors residing on ring data structures in the NIC memory. The processor indicates whether the data segment involved in a transfer is to be written to the buffer by setting an appropriate flag indicator in the descriptor for the transfer. By this mechanism, the processor obtains fast access to important data such as packet headers and descriptors from host memory, so that packet processing performance is improved.
Other aspects, features, and advantages of the present invention are disclosed in the detailed description that follows.
REFERENCES:
patent: 5398245 (1995-03-01), Harriman, Jr.
patent: 5488724 (1996-01-01), Firoozmand
patent: 5651002 (1997-07-01), Seters et al.
patent: 6173333 (2001-01-01), Jolitz et al.
Brown Michael K.
Chieffo Paul
Platko John J.
3Com Corporation
Lee Thomas
Park Iiwoo
Weingarten Schurgin, Gagnebin & Lebovici LLP
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