Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-08-30
1998-09-01
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711113, G06F 1200
Patent
active
058025600
ABSTRACT:
A method and apparatus for use in computer systems utilizes a memory chip employing multiple distributed SRAM caches directly linked to a single DRAM main memory block. Each cache is directly linked to a different bus. Each chip further contains a partially distributed arbitration and control circuit for implementing cache policy and arbitrating memory refresh cycles.
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Heisler Dion Nickolas
Heisler Doyle James
Joseph James Dean
Burton, Esq. Carol W.
Kubida, Esq. William J.
Langjahr David
Meza, Esq. Peter J.
Ramton International Corporation
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