Multibank dram system controlled by multiple dram controllers wi

Details Multibank dram system controlled by multiple dram controllers wi Multibank dram system controlled by multiple dram controllers wi

1996-12-09

1999-04-06

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

711105, G06F 1214

Patent

active

058931589

ABSTRACT:
In the control of DRAM having a plurality of banks by a pair of memory controllers, a high rate operation is enabled by a pipeline control even during an exchange of the privilege to use a memory. Specifically, a system memory 11 having a plurality of banks is shared by a memory controller 12 and an external device 13 for pipeline control. Both the memory controller 12 and the external device 13 include a monitor circuit which monitors an address and a control signal delivered by the counterpart. When the privilege to use a memory is to be transferred, a bank which is currently active is examined, and such access is immediately allowed when the access is to a bank which is not active. When the access is to a bank which is currently active, a standby interval is provided, and the access is allowed after its transition to an inactive condition. A pipeline control is enabled even during a changeover of the privilege to use the memory, thus allowing a high rate operation of a computer system.

REFERENCES:
patent: 5319768 (1994-06-01), Rastegar
patent: 5465344 (1995-11-01), Hirai et al.
patent: 5631871 (1997-05-01), Park
patent: 5659711 (1997-08-01), Sugita
patent: 5737569 (1996-03-01), Nadir et al.
patent: 5745913 (1996-08-01), Pattin et al.

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