Multi-way select instructions using accumulated condition codes

Details Multi-way select instructions using accumulated condition codes Multi-way select instructions using accumulated condition codes

2006-04-11

2006-04-11

Ellis, Richard L. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Logic operation instruction processing

C712S005000, C708S236000

Reexamination Certificate

active

07028171

ABSTRACT:
The present invention relates to a method and system for providing an N-way select instruction in a processor. Specifically, a method for providing an N-way select instruction includes decoding an instruction as an N-way select instruction. The method also includes selecting at least one pair of source operands from a plurality of instruction operands using information from a plurality of parallel control registers. The method, further includes selecting a final source operand from each of the selected at least one pair of source operands, and outputting each of the selected final source operands. In general, any N-way select instruction will have M=log2N stages of operation.

REFERENCES:
patent: 5802336 (1998-09-01), Peleg et al.

Affiliated with

Also associated with

Rating

Multi-way select instructions using accumulated condition codes does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-way select instructions using accumulated condition codes, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-way select instructions using accumulated condition codes will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3550170