Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-04-20
2001-02-06
Cabeca, John W. (Department: 2752)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S154000
Reexamination Certificate
active
06185657
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to processors and memory, and more particularly to multi-way cache memory.
BACKGROUND OF THE INVENTION
Lower power consumption has been gaining importance in microprocessor and microcontroller design due to wide spread use of portable and handheld applications. A typical embedded control system will generally include a central processing unit (CPU) and a variety of different types of memory and peripheral devices. The different types of memory may be external to an integrated circuit having the microcontroller, and/or on the same integrated circuit, and may include cache memory, ROM (read only memory), and a variety of SRAM (static random access memory) devices.
A significant amount of energy and time is required to access a large external main memory. Therefore, a smaller, faster, and more efficient memory, sometimes referred to as a cache, may be used on the integrated circuit to reduce the number of accesses to the main memory. To keep the size of the integrated circuit as small as possible, only as much memory as is necessary is included onboard the integrated circuit.
A cache TAG is frequently used to increase the performance of the cache. The cache TAG receives a TAG address that is provided by the microprocessor and determines if the requested instructions and/or data are present in the cache memory. If a requested instruction is not located in the cache, the microprocessor must then retrieve the instruction from the main memory. When an instruction is written into the cache, the higher order bits of the address of the instruction are stored in a TAG array. The cache TAG also has a comparator that compares a processor generated address to the TAG address. If the TAG address and the processor generated address are the same, a cache “hit” occurs, and a match signal is provided by the cache TAG, indicating that the requested data is located in the cache memory. If the processor generated address and the TAG address are not the same, a cache “miss” occurs, and the match signal indicates that the requested data is not located in the cache memory. In addition, a valid bit may be set as a part of the TAG address for qualifying a valid hit of the stored TAG address during a compare cycle of the cache.
With conventional cache approaches, in many applications, cache efficiency may be negatively affected by conflicting access requirements leading to many cache misses and external memory accesses. In addition, in low power applications, a premium is placed on efficient power management for processing resources. It would be desirable for a cache memory to provide increased processing efficiency, e.g. higher cache hit rates, combined with lower power consumption.
Accordingly, there is a need for an improved cache apparatus and method.
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Motorola Inc., “MC88110 Second Generation RISC Microprocessor User's Manual”, Section 6, pp. 6-1 through 6-46 (1991).
Cabeca John W.
Motorola Inc.
Tran Denise
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