Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1998-06-02
2000-10-10
Nguyen, Hiep T.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711129, 711173, 365 49, G06F 1208
Patent
active
06131143&
ABSTRACT:
An associative storage type cache memory is disclosed, which comprises a decoder for decoding an entry address designated by a data processing unit, a first tag memory for storing higher-order bits of an address tag, the first tag memory being common to multiple ways, second tag memories for storing lower-order bits of the address tag, the second tag memories corresponding to the individual ways, data memories for storing data designated by an address consisting of the contents of the first and second tag memories, a first comparator for comparing higher-order bits of a tag address with the contents of the first tag memory, second comparators for comparing lower-order bits of the tag address with the contents of the second tag memories, respectively, and a way selector for selecting data from the data memories corresponding to hit signals received from the first and second comparators and outputting the selected data.
REFERENCES:
patent: 5206941 (1993-04-01), Eikill et al.
patent: 5325504 (1994-06-01), Tipley et al.
patent: 5684976 (1997-11-01), Soheili-Arasi et al.
Japanese Office Action, dated Jun. 22, 1999, with English Language Translation of Japanese Examiner's comments.
NEC Corporation
Nguyen Hiep T.
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