Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol
Reexamination Certificate
1996-07-23
2002-04-02
Wiley, David (Department: 2155)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Protocol
Reexamination Certificate
active
06366972
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to data processing systems, and particularly to a configuration for a high-speed, multi-user bus structure to attenuate noise attributable to ringing and signal reflections on the bus.
As clock speeds used in computing and data processing systems increase (e.g., in the 100 Mhz range or higher), it is becoming important to give attention to the electrical characteristics of the medium used to communicate information between two or more elements of the system. Higher computing and communicating speeds have shrunk pulse widths, making it important that the integrity (i.e., sharpness of) pulse transitions, the rise and fall times of those pulses, and the higher frequencies forming those transitions be maintained.
Corruption of the integrity of a pulse can be attributed to a number of factors that are primarily found in the particular environment, among them impedance discontinuities in the signal path which can lead to pulse distortion itself, as well as serving as the source of ringing, and reflections which can further attack pulse integrity. (Ringing is that distortion following a major transition, and is usually in the form of a superimposed, clamped oscillatory waveform. Reflection is that phenomenon that occurs when a pulse encounters a discontinuity or different transmission medium, producing a reflected version of the pulse on the original transmission medium.) Matching the different impedances encountered in the signal path between the source and destination of the pulse (including the source output and destination input impedances) is one tried and true method of improving signal quality. But, in a real world environment it is very difficult, if not at times impossible, to match impedances sufficiently. Discontinuities imposed by connectors, inexact input or output impedances, and other factors can and do operate to sully data signals (i.e., pulse construction). As a result, the pulse may take longer to achieve a recognizable voltage level.
The mechanical construction and packaging of data processing and computing systems often use multiple printed-wiring circuit boards (PWBs) that communicatively connect to one another by a bus structure of form or another. One popular packaging construction provides removable connection of the PWBs to a backplane, or like assembly that carries the bus structure. Preferably, the signal paths between the bus structure and whatever driver/receiver circuit devices are employed by the users of the bus structure, the PWBs, should be kept short for improved electrical characteristics of high-speed signals. Signal paths that are too long can lead to ringing, resulting in excessive pulse settling times. Unfortunately, in some cases it may not be physically possible to use an electrically short signal path between the driver/receiver of a PWB and the bus structure due to routing restraints on the PWB, or perhaps because of the particular wiring of the bus in the backplane for connecting multiple PWBs.
One solution often used to reduce ringing and reflections is to place a series terminating resistance in the signal path proximate the driver/receiver element of the PWB. (Shared bus structures typically employ a tri-state device that operates in one of two mutually-exclusive modes: to drive signals onto, or to receive signals from, the bus structure. For that reason they are referred to herein as “driver/receivers.”) This solution is illustrated in
FIG. 1
, which shows one bit line of an N-bit communication bus
14
with four users. The bus
14
is divided into bus portions
14
′ to illustrate the equivalent transmission line segments of the bus that extend between PWB connectors
13
. The signal lines from the connectors to the driver/receiver devices
12
on the PWB are shown as segments or transmission line equivalents
15
.
FIG. 1
shows resistors R placed serially in the signal path, preferably near or at the output/input of the driver/receiver devices
12
. This configuration is applicable to active devices having driver portion output impedances less than the characteristic impedance of the bus and PWB and a receiver portion input impedance much greater than the PWB characteristic impedance. Systems using CMOS devices and some TTL designs, for example, often use this solution. For devices having a low input impedance, such as emitter-coupled logic (ECL), parallel terminations are used to help reduce ringing and reflections. (i.e., the series resistors R in
FIG. 1
are removed, and the outer ends left and right in
FIG. 1
are tied to AC ground through appropriate resistances.) Whichever solution is used, routing requirements may cause the various paths forming the bus portions
14
′ or the PWB paths
15
to be on the order of several inches in length, creating path impedances that are difficult to match by the resistances R. In such cases, any meaningful reduction of the ringing and excessive settling on the bus by such techniques is lost. But even with proper impedance matching, ringing and settling can still occur in amounts that unduly affect performance.
SUMMARY OF THE INVENTION
The present invention provides a bus structure and configuration that operates to significantly reduce ringing and settling times of signalling used for high-speed data communication in a digital processing or computing system.
According to the present invention, the bus structure is divided into a number of bus portions, one bus portion for each user of the bus structure. The bus portions are connected together through an impedance matching network to form a star topology. The particular configuration of the impedance matching network depends upon the number of users connected to and using the bus structure. In the preferred embodiment of the invention the impedance of the network is primarily resistive. The values of the resistors used are a function of the design impedance of the connecting paths, i.e., the characteristic impedance of the signal paths between the driver/receiver device and the bus structure, and that of the signal paths forming the bus, and the input/output impedances of the active devices, the receivers/drivers, that drive and receive from the bus structure.
The invention has the advantage of achieving the reduction of ringing, signal reflections, and excessive settling time by meaningful amounts over that of prior systems.
These and other advantages and features of the present invention will become apparent to those skilled in this art upon a reading of the following description of the invention which should be taken in conjunction with the accompanying drawings.
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patent: 4736124 (1988-04-01), McFarland, Jr.
patent: 4763087 (1988-08-01), Schrader
patent: 4912724 (1990-03-01), Wilson
patent: 5216667 (1993-06-01), Chu et al.
patent: 5347177 (1994-09-01), Lipp
patent: 5359235 (1994-10-01), Coyle et al.
patent: 5448591 (1995-09-01), Goodrich
patent: 5463359 (1995-10-01), Heaton
patent: 5548734 (1996-08-01), Kolinski et al.
patent: 5638402 (1997-06-01), Osaka et al.
Grebenkemper C. John
Nguyen Dong
Compaq Computer Corporation
Leah Sherry Oppenheimer Wolff & Donnelly
Wiley David
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