Multi-tiered interrupt structure with global interrupt enablemen

Details Multi-tiered interrupt structure with global interrupt enablemen Multi-tiered interrupt structure with global interrupt enablemen

1997-12-18

1999-11-09

Donaghue, Larry D.

Electrical computers and digital data processing systems: input/

Interrupt processing

Interrupt queuing

709224, G06F 946, G06F 1516

Patent

active

059833084

ABSTRACT:
An interrupt system having three tiers is provided. The first tier includes individual interrupt and enable registers, each of which provides multiple local interrupt signals in response to various events in a multiport switch. Local enable signals are supplied to the individual interrupt and enable registers to enable the local interrupt signals to be written into a global interrupt status register that provides the second tier of the interrupt system. The global interrupt status register produces several global interrupt signals, each of which represents one of the individual interrupt and enable registers. The third tier of the interrupt system includes a switch command register that generates an interrupt pending signal if any one of the global interrupt signals is produced. A global enable signal provided by the host processor enables the switch command register to produce an interrupt request signal to be supplied to a host processor.

REFERENCES:
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patent: 5701495 (1997-12-01), Arndt et al.
patent: 5771374 (1998-06-01), Burshtein et al.
patent: 5819112 (1998-10-01), Kusters
patent: 5850555 (1998-12-01), Qureshi et al.
patent: 5875343 (1999-02-01), Binford et al.
patent: 5892957 (1999-04-01), Normoyle et al.

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