Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1995-06-02
1998-10-06
Tokar, Michael J.
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 41, H03K 738, H03K 19177
Patent
active
058182543
ABSTRACT:
A hierarchical switch matrix in a very high-density programmable logic device (CPLD) interconnects a multiplicity of programmable logic blocks in the CPLD. A new level of functionality coupled with high speed is provided by the hierarchical switch matrix. The hierarchical switch matrix includes three levels, a global switch matrix, a segment switch matrix and a block switch matrix. The block switch matrix provides a high speed signal path for signals within a programmable logic block. The segment switch matrix provides a high speed means of communication for signals within a segment, while the global switch matrix provides a high speed path for communication between segments. The hierarchical switch matrix of this invention provides a fixed, path independent, uniform, predictable and deterministic time delay for each group of signals routed through the hierarchical switch matrix.
REFERENCES:
patent: 4742252 (1988-05-01), Agrawal
patent: 4758746 (1988-07-01), Birkner et al.
patent: 4771285 (1988-09-01), Agrawal et al.
patent: 4789951 (1988-12-01), Birkner et al.
patent: 4931671 (1990-06-01), Agrawal
patent: 4963768 (1990-10-01), Agrawal et al.
patent: 5015884 (1991-05-01), Agrawal et al.
patent: 5130574 (1992-07-01), Shen et al.
patent: 5151623 (1992-09-01), Agrawal
patent: 5191243 (1993-03-01), Shen et al.
patent: 5204556 (1993-04-01), Shankar
patent: 5220214 (1993-06-01), Pedersen
patent: 5243238 (1993-09-01), Kean
patent: 5258668 (1993-11-01), Cliff et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5371422 (1994-12-01), Patel
patent: 5394033 (1995-02-01), Tsui
patent: 5455525 (1995-10-01), Ho et al.
patent: 5457410 (1995-10-01), Ting
patent: 5521529 (1996-05-01), Agrawal et al.
Psing-Tsung Wang, et al., "A High Performance FPGA with Hierarchial Interconnection Structure", vol. 4 of 6, 30 May 1994, IEEE, pp. 239-242, XP000493185.
Stan Kopec et al., "Obtaining 70MHz Performance in the MAX Architecture", Electronic Engineering, vol. 63, No. 773, May 1991, pp. 69, 70, 72, 74.
Doug Conner, "PLD Architectures Require Scrutiny", EDN Electrical Design News, vol. 34, No. 20, Sep. 28, 1989, pp. 91, 93, 94, 96, 98, 100.
Steve Landry, "Application--Specific IC's Relying on RAM, Implement Almost any Logic Function", Electronic Design, vol. 33, No. 25, Oct. 1985, pp. 123-128, 130.
"Introduction to pLSI and ispLSI", pLSI and ispLSI Databook & Handbook, Lattice Semiconductor Corp., (undated), pp. 1-1 through 1-8.
"pLSI 1032 programmable Large Scale Integration", Rev. A., Lattice Semiconductor Corp., Jan. 1992, pp. 2-1 through 2-29.
"EPM7032 EPLD, High-Performance 32-Macrocell Device", Data Sheet, Altera Corp., Ver. 1, Dec. 1991, pp. 1-15.
Om P. Agrawal, "AMD's Next Generation MACH.TM.3xx/4xx Family Breaks New PLD Density/Speed Barrier", Conference Record, Wescon 92, Nov. 1992, pp. 100-106.
Raymond Leung et al., "A 7.5 ns 350mW BiCMOS PAL.RTM.-type Device", Proceedings of the 1989 IEEE Custom Integrated Circuits Conference, May 1989 pp. 5.6.1-5.6.4.
Agrawal Om P.
Sharpe-Geisler Bradley A.
Advanced Micro Devices , Inc.
Kwok Edward C.
Roseen Richard
Tokar Michael J.
LandOfFree
Multi-tiered hierarchical high speed switch matrix structure for does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-tiered hierarchical high speed switch matrix structure for, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-tiered hierarchical high speed switch matrix structure for will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-82368