Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-05-01
1998-07-28
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711113, 711160, G06F 1208
Patent
active
057874662
ABSTRACT:
A multi-tier cache system and a method for implementing the multi-tier cache system is disclosed. The multi-tier cache system has a small cache in random access memory (RAM) that is managed in a Least Recent Used (LRU) fashion. The RAM cache is a subset of a much larger non-volatile cache on rotating magnetic media (e.g., a hard disk drive). The non-volatile cache is, in turn a subset of a local CD-ROM or of a CD-ROM or mass storage device controlled by a server system. In a preferred embodiment of the invention, a heuristic technique is employed to establish a RAM cache of optimum size within the system memory. Also in a preferred embodiment, the RAM cache is made up of multiple identically-sized sub-blocks. A small amount of RAM is utilized to maintain a table which implements a Least Recently Used (LRU) RAM cache purging scheme. A hashing mechanism is employed to search for the "bucket" within the RAM cache in which the requested data may be located. If the requested data is in the RAM cache, the request is satisfied with that data. If the requested data is not in the RAM cache, the least recently used sub-block is purged from the cache if the cache is full, and the RAM cache is updated from the non-volatile cache whenever possible, and from the cached storage device when the non-volatile cache does not contain the requested data.
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King , Jr. Conley B.
Kubida William J.
Langley Stuart T.
Sun Microsystems Inc.
Swann Tod R.
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