Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2001-04-03
2004-09-07
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C710S008000, C710S010000, C714S030000, C714S738000, C714S742000, C711S170000
Reexamination Certificate
active
06789160
ABSTRACT:
BACKGROUND OF INVENTION
Computer processors comprise arithmetic, logic, and control circuitry that interpret and execute instructions from a computer program. Referring to
FIG. 1
, a typical computer system includes a microprocessor (
22
) having, among other things, a CPU (
24
), a memory controller (
26
), and an on-chip cache memory (
30
). The microprocessor (
22
) is connected to external cache memory (
32
) and a main memory (
34
) that both hold data and program instructions to be executed by the microprocessor (
22
). Internally, the execution of program instructions is carried out by the CPU (
24
). Data needed by the CPU (
24
) to carry out an instruction are fetched by the memory controller (
26
) and loaded into internal registers (
28
) of the CPU (
24
). Upon command from the CPU (
24
) requiring memory data, the fast on-chip cache memory (
30
) is searched. If the data is not found, then the external cache memory (
32
) and the slow main memory (
34
) is searched in turn using the memory controller (
26
). Finding the data in the cache memory is referred to as a “hit.” Not finding the data in the cache memory is referred to as a “miss.”
The time between when a CPU requests data and when the data is retrieved and available for use by the CPU is termed the “latency” of the system. If requested data is found in cache memory, i.e., a data hit occurs, the requested data can be accessed at the speed of the cache and the latency of the system is reduced. If, on the other hand, the data is not found in cache, i.e., a data miss occurs, and thus the data must be retrieved from the external cache or the main memory at increased latencies.
Multi-threaded processors exist such that when functions performed by a given thread in a processor come to a halt, e.g., when awaiting data to be returned from main memory after a read operation, the processor can perform other functions on a different thread in the meantime. These processors embody the ability to instantaneously switch execution flow, for example, from a Thread A to a Thread B, when Thread A is blocked from execution. As mentioned above, most often execution is blocked by waiting for an input-output (I/O) operation (typically, a read/write operation) to complete.
Random Access Storage Devices are the most common secondary storage device and allow data to be stored in any order, i.e., randomly, and retrieved in any order. Some examples of random access storage device are hard disks, CDROM, DVD-ROM, and floppy disks. Typically, random access devices have large storage capacity and they access data very quickly. The data is stored in random access storage devices on a sector or logical block basis. The addressing of the data on the sector for retrieval is done using two mechanisms. A hard disk contains cylinders, heads, and sectors, so the data can be addressed by cylinder, head, and sector number. Alternatively, recent hard disks have mechanisms that allow logical block addressing. That is, the whole capacity of the drive is split into a stream of fixed size blocks called logical blocks and addressed using logical block numbers.
In computer systems, such random access storage devices are connected to a host bus adapter (HBA). The HBA allows communication with the storage device using well known protocols to get the data in and out of the device. The protocol used dictates the number of devices that can be connected or addressed. The connected devices are called targets.
It is possible that a target could be manufactured with multiple logical units contained within the target. These logical units within a target could represent a homogenous or heterogeneous set of devices. For example, a target could have 4 logical units and each logical unit could be a individual storage device with some capacity associated with it.
The most fundamental program resident on any computer is the operating system (OS). Various operating systems exist in the market place, including Solaris™ from Sun Microsystems Inc., Palo Alto, Calif. (Sun Microsystems), Macintosh® from Apple Computer, Inc., Cupertino, Calif., Windows® 95/98 and Windows NT®, from Microsoft Corporation, Redmond, Wash., and Linux. A Solaris™ driver allows random access storage devices to be addressed based on a device node created by the driver framework. The logical device node exported to the users is of the form:
/dev/rdsk/c?t?d?s?
Where c? indicates the letter “c” followed by a number representing the HBA's number; t? indicates the letter “t” followed by a number representing the target number; d? indicates the letter “d” followed by a number representing the logical unit number (LUN); s? indicates the letter “s” followed by the partition number within the device addressed using the controller number, target number and lun number.
Typically, the partitions are specified by the operating system under which the device is used. This information is specified in a known sector or logical block so that the driver can understand the boundaries of each partition, validate the request to read or write a sector, and export the nodes required to address the information within the partition. Also, such partitioning gives a user the flexibility to split a high capacity device into logical sections so that the data can be logically segregated. The way that the disk is partitioned is left up to the user to decide and is done using available tools for the given operating system. This partition information is called Volume Table of Contents (VTOC) under the Solaris™ operating system. The VTOC is stored in the first sector of the disk as part of the label information maintained. In Solaris™, typically slice #2 is used to address the whole device.
SUMMARY OF INVENTION
In general, in one aspect, the present invention involves a method for qualifying random access storage devices comprising determining qualification parameters for each of the random access storage devices; determining a configuration for each of the random access storage devices; and qualifying each of the random access storage devices based on the determined qualification parameters and configuration.
In general, in one aspect, the present invention involves a tool for qualifying random access storage devices comprising a parser for determining qualification parameters; a machine configuration collector for determining random access storage device configuration; and a thread spawner for qualifying each of the random access storage devices based on the determined qualification parameters and configuration
In general, in one aspect, the present invention involves a tool for qualifying random access storage devices comprising means for determining qualification parameters for each of the random access storage devices; means for determining a configuration for each of the random access storage devices; and means for qualifying each of the random access storage devices based on the determined qualification parameters and configuration.
In general, in one aspect, the present invention involves a tool for qualifying random access storage devices, comprising a processor in communication with the random access storage devices; and a program executable on the processor. The program is for determining qualification parameters of each of the random access storage devices; determining a configuration for each of the random access storage devices; and qualifying each of the random access storage devices based on the determined qualification parameters and configuration.
In general, in one aspect, the present invention involves a multi-threaded tool for qualifying random access storage devices, comprising a processor in communication with the random access storage devices; and a program executable on the processor. The program comprising a command line parser for determining qualification parameters from a command line; a device discovery algorithm for determining a configuration for each of the random access storage devices; an exclude file parser for excluding random access storage
Osha & May L.L.P.
Padmanabhan Mano
Song Jasmine
Sun Microsystems Inc.
LandOfFree
Multi-threaded random access storage device qualification tool does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-threaded random access storage device qualification tool, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-threaded random access storage device qualification tool will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3252626