Multi-threaded processor architecture

Details Multi-threaded processor architecture Multi-threaded processor architecture

2006-09-07

2011-10-25

Kindred, Alford (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Reexamination Certificate

active

08046567

ABSTRACT:
A multi-threaded processor that is capable of responding to, and processing, multiple low-latency-tolerant events concurrently and while using relatively slow, low-power memories is disclosed. The illustrative embodiment comprises a multi-threaded processor, which itself comprises a context controller and a plurality of hardware contexts. Each hardware context is capable of storing the current state of one thread in a form that enables the processor to quickly switch to or from the execution of that thread. To enable the processor to be capable of responding to low-latency-tolerant events quickly, each thread—and, therefore, each hardware context is prioritized—depending on the latency tolerance of the thread responding to the event.

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Parekh, Sujay, et al., “Thread-Sensitive Scheduling for SMT Processors.” Department of Computer Science & Engineering, University of Washington, 2000.
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Raasch, Steven E., et al. “Applications of Thread Prioritization in SMT Processors.” Proc. 1999 Workshop on Multithreaded Execution and Compilation, Jan. 1999.

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