Multi-threaded embedded processor using deterministic...

Details Multi-threaded embedded processor using deterministic... Multi-threaded embedded processor using deterministic...

2006-06-13

2006-06-13

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

07062606

ABSTRACT:
A multi-threaded embedded processor that includes an on-chip deterministic (e.g., scratch or locked cache) memory that persistently stores all instructions associated with one or more pre-selected high-use threads. The processor executes general (non-selected) threads by reading instructions from an inexpensive external memory, e.g., by way of an on-chip standard cache memory, or using other potentially slow, non-deterministic operation such as direct execution from that external memory that can cause the processor to stall while waiting for instructions to arrive. When a cache miss or other blocking event occurs during execution of a general thread, the processor switches to the pre-selected thread, whose execution with zero or minimal delay is guaranteed by the deterministic memory, thereby utilizing otherwise wasted processor cycles until the blocking event is complete.

REFERENCES:
patent: 6779065 (2004-08-01), Murty et al.
patent: 2002/0018486 (2002-02-01), Musoll et al.
patent: 2003/0067913 (2003-04-01), Georgiou et al.

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