Multi-terminal chalcogenide logic circuits

Static information storage and retrieval – Systems using particular element – Amorphous

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S148000, C326S052000, C326S104000

Reexamination Certificate

active

07969769

ABSTRACT:
Logic circuits are disclosed that include one or more three-terminal chalcogenide devices. The three-terminal chalcogenide devices are electrically interconnected and configured to perform one or more logic operations, including AND, OR, NOT, NAND, NOR, XOR, and XNOR. Embodiments include series and parallel configurations of three-terminal chalcogenide devices. The chalcogenide devices include a chalcogenide switching material as the working medium along with three electrical terminals in electrical communication therewith.In one embodiment, the circuits include one or more input terminals, one or more output terminals, and a clock terminal. The input terminals receive one or more input signals and deliver them to the circuit for processing according to a logic operation. Upon conclusion of processing, the output of the circuit is provided to the output terminal. The clock terminal delivers a clock signal to facilitate operation of the three-terminal devices included in the instant circuits. In one embodiment, the clock signal includes an ON cycle and an OFF cycle, where the circuit performs a logic operation during the ON cycle and any three-terminal devices that are switched to the conductive state during the ON cycle are returned to their resistive state during the OFF cycle.

REFERENCES:
patent: 5166758 (1992-11-01), Ovshinsky et al.
patent: 5296716 (1994-03-01), Ovshinsky et al.
patent: 5534711 (1996-07-01), Ovshinsky et al.
patent: 5536947 (1996-07-01), Klersy et al.
patent: 5543737 (1996-08-01), Ovshinsky
patent: 5596522 (1997-01-01), Ovshinsky et al.
patent: 5694054 (1997-12-01), Ovshinsky et al.
patent: 5694146 (1997-12-01), Ovshinsky et al.
patent: 5714768 (1998-02-01), Ovshinsky et al.
patent: 5757446 (1998-05-01), Ovshinsky et al.
patent: 6087674 (2000-07-01), Ovshinsky et al.
patent: 6671710 (2003-12-01), Ovshinsky et al.
patent: 6714954 (2004-03-01), Ovshinsky et al.
patent: 6963893 (2005-11-01), Ovshinsky et al.
patent: 6967344 (2005-11-01), Ovshinsky et al.
patent: 6969867 (2005-11-01), Ovshinsky
patent: 6999953 (2006-02-01), Ovhsinsky
patent: 7186998 (2007-03-01), Ovshinsky et al.
patent: 2007/0096071 (2007-05-01), Kordus et al.
patent: 2007/0267623 (2007-11-01), Ovshinsky
Ovshinsky, “Reversible Electrical Switching Phenomena in Disordered Structures,” Nov. 11, 1968. Physical Review Letters, vol. 21, No. 20, pp. 1450-1455.
Ovshinsky et al., “Amorphous Semiconductors for Switching, Memory, and Imaging Applications,” Feb. 1993. IEEE Transactions on Electron Devices, Col. ED-20, No. 2, pp. 91-105.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Multi-terminal chalcogenide logic circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-terminal chalcogenide logic circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-terminal chalcogenide logic circuits will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2689355

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.