Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2001-12-26
2004-06-15
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257SE21508, C257SE23069, C385S016000, C385S017000, C385S018000, C427S096400, C427S098300, C427S099300
Reexamination Certificate
active
06750547
ABSTRACT:
BACKGROUND
The present invention relates generally to multi-substrate microelectronic packages, such as stacked microelectronic substrate packages, and methods for manufacturing such packages. Conventional packaged semiconductor products typically include a microelectronic die at least partially surrounded by a protective encapsulant. The die within the encapsulant is electrically connected to external terminals accessible from outside the encapsulant for coupling the die to other microelectronic components. The coupled microelectronic components can be housed in a computer, telecommunication device, or other consumer or industrial electronic product.
As the size of the electronic products into which the microelectronic packages are incorporated has decreased, it has become necessary to decrease the size of the packages. One approach to reducing the size of the microelectronic packages is to stack one die on top of another within the package, which reduces the total planform area or footprint occupied by the two dies. The stacked dies within the package are then electrically connected to each other with wire bonds. One drawback with this approach is that wire-bonding the dies can place stresses on the dies that can ultimately cause the dies to fail. Another drawback is that the wire bonds can break loose from the dies. Still another drawback is that signals may travel too slowly between the dies, due to the length of the wire bonds. Yet another drawback is that the individual dies can be difficult to handle during the stacking and bonding operation, due to the relatively small size of the dies.
SUMMARY
The present invention is directed toward multi-substrate microelectronic packages and methods for forming such packages. A method in accordance with one aspect of the invention includes positioning a first microelectronic substrate proximate to a second microelectronic substrate and coupling the microelectronic substrates to form a substrate assembly. Each microelectronic substrate has a first surface with a connection site, and a second surface facing opposite the first surface. The microelectronic substrates are coupled such that the first surface of the first microelectronic substrate faces toward the second surface of the second microelectronic substrate. The method can further include sequentially disposing at least first and second portions of a conductive material on the substrate assembly to build up a conductive structure connected between the connection sites of the microelectronic substrates.
In a further aspect of the invention, a plurality of second microelectronic substrates can be attached to a corresponding plurality of first microelectronic substrates while the first microelectronic substrates are attached to each other to define at least a portion of a microelectronic wafer. Conductive material can then be sequentially disposed to connect connection sites of the first microelectronic substrates with connection sites of the second microelectronic substrates. The resulting substrate assemblies are then separated from each other.
The invention is also directed toward a microelectronic device package. In one aspect of the invention, the device package can include a first microelectronic substrate having a first surface with a first connection site, and a second surface facing opposite the first surface. The package can further include a second microelectronic substrate having a first surface with a second connection site and a second surface facing opposite the first surface. The second microelectronic substrate can be coupled to the first microelectronic substrate with the second surface of the second microelectronic substrate facing toward the first surface of the first microelectronic substrate. A conformal conductive link can be coupled between the first and second connection sites, and can conform at least generally to a contour of the substrate assembly immediately adjacent to the conformal conductive link. In a further aspect of the invention, an adhesive film can be disposed between the first and second microelectronic substrates. In still a further aspect of the invention, the first microelectronic substrate can have an exposed edge between the first and second surfaces. In yet a further aspect of the invention, the microelectronic device package can be positioned in the housing of an electronic device.
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Jeung Boon Suan
Poo Chia Yong
Waf Low Siu
Micro)n Technology, Inc.
Nelms David
Perkins Coie LLP
Tran Mai-Huong
LandOfFree
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