Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2002-08-12
2004-01-20
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S691000, C257S708000, C257S635000, C257S621000, C257S664000
Reexamination Certificate
active
06680530
ABSTRACT:
TECHNICAL FIELD
The field of the invention is that of packaging integrated circuits for high speed applications.
BACKGROUND OF THE INVENTION
In the field of integrated circuit packaging, high performance packages are often formed from layers of ceramic that are pressed together with metal embedded in it. The embedded metal is positioned so that it forms a set of interconnections in the final product, carrying signals from the substrate to the chips mounted on its top surface. Conventionally, in order to have the minimum number of connections, any vertical transitions that are required will be accomplished in a single step. An example is given in
FIG. 4
, in which a lower horizontal interconnect
152
′ is connected to an upper interconnect
152
′ through via
20
151
′.
Those skilled in the art are aware that an impedance mismatch is present at the transition between the horizontal runs and the vertical, caused by geometry and by a difference in materials. The magnitude of this impedance mismatch depends on the frequency of the signal being carried and, in some cases, can result in reflections that effectively cancel an incoming signal or feed back into other parts of the circuit.
As signal switching speeds have increased, the art has devised more sophisticated and expensive structures to carry signals and remove heat to and from integrated circuits. With present technology, it is not possible to run signals in the gigabit range through the bulk of a ceramic chip carrier with acceptable frequency response. The art has been required to use connectors attached to transmission lines running in a single plane, at considerable cost and subject to tight space limits.
Edge or surface mount connectors have been used to provide acceptable performance, but cost more to implement and only a very limited number can be used due to real estate constraints on the top surface.
SUMMARY OF THE INVENTION
The invention relates to a multi-layer chip carrier that makes vertical transitions in signal paths through a number of small steps, rather than a single larger step.
A feature of the invention is the use of a set of horizontal signal lines extending through the package and disposed on the interlayer surfaces of the set of ceramic sheets, in which at least one of the signal lines has at least three horizontal segments connected by at least two vias.
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Dyckman Warren D.
Pillai Edward R.
Cioffi James J.
Clark Jasmine
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