Multi-step spacer formation of semiconductor devices

Details Multi-step spacer formation of semiconductor devices Multi-step spacer formation of semiconductor devices

1999-03-23

2001-06-05

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S305000, C438S279000

Reexamination Certificate

active

06242334

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a semiconductor device, and more particularly to a method for forming a logic device using multi-step sidewall spacer formation.
2. Description of the Prior Art
For logic devices of modern integrated circuits, the narrow line effect of the titanium-salicide technology becomes a bottleneck while the dimension of the devices has been rapidly decreasing. In order to overcome this problem, as shown in
FIGS. 1A and 1B
, an over etch process of the sidewall spacer
180
A around the gate (
160
,
140
, and
120
) is usually applied, so that the top surface of the sidewall spacer
180
A is over etched (about 500 angstroms) below the top surface of the gate. Unfortunately, the width of the sidewall spacer
180
A is also accordingly reduced, resulting a sidewall spacer too narrow for the purpose of isolation.
In the prior art, in order to solve the aforementioned dilemma, a thicker spacer (e.g. 1500-2000 angstroms compared to conventional 1000 angstroms) is used, which results in a sidewall spacer with enough width for isolation. However, this solution is not feasible for fabricating devices with dimension below 0.18 micrometer due to lack of space between gates. Further, width of the lightly doped drain (LDD) increases accordingly, which causes high resistivity and low speed for the devices. Furthermore, this solution causes top gate polysilicon (TGP) corner loss owing to heavy Ar bombardment during long spacer etch.
For the foregoing reasons, there is a need for a method of forming a logic device in the integrated circuits whose sidewall spacer has enough width for isolation without aforementioned disadvantages.
SUMMARY OF THE INVENTION
In accordance with the present invention, a multi-step method is provided for forming a semiconductor device with overetched spacer that is feasible for the logic devices.
Another purpose of the present invention is to provide a method for forming logic devices in the integrated circuits, wherein the sidewall spacer has enough width for the purpose of isolation.
Furthermore, the present invention provides a method for forming logic devices feasible for fabricating semiconductor devices with dimension below 0.18 micrometer without scarifying the resistivity of the lightly-doped drain (LDD) structure or causing top gate polysilicon (TGP) corner loss owing to heavy Ar bombardment during spacer etch.
In one embodiment, a semiconductor substrate with a gate oxide layer formed on the substrate is firstly provided, followed by forming a polysilicon layer on the gate oxide layer. Next, a photoresist layer is formed on the polysilicon layer to define a gate area, and the polysilicon layer and the gate oxide layer are then anisotropically etched using the photoresist layer as a mask until surface of the substrate is exposed. After forming a tetraethoxysilane (TEOS) layer on the exposed substrate and on the etched polysilicon layer and gate oxide layer, and subsequently forming a first silicon nitride layer on the TEOS layer, the first silicon nitride dielectric layer is anisotropically etched until the TEOS layer is exposed, thereby forming a first sidewall spacer on the sidewall of the TEOS layer around the gate area. A second silicon nitride layer is formed over the exposed TEOS layer and the first sidewall spacer. Finally, the second silicon nitride layer and the first sidewall spacer are anisotropically etched so that a second sidewall spacer is formed on sidewall of the first sidewall spacer, wherein the top surface of the first and the second sidewall spacer is below the top surface of the TEOS layer around the gate area.


REFERENCES:
patent: 5714413 (1998-02-01), Brigh et al.
patent: 5882973 (1999-03-01), Gardner et al.
patent: 5908315 (1999-06-01), Gardner et al.

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