Multi-step programming of E fuse cells

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

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C365S225700, C365S096000, C327S525000

Reexamination Certificate

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07834659

ABSTRACT:
E-fuses in an E-fuse memory array are programmed by applying a first programming pulse to a plurality of E-fuses to program the plurality of E-fuses to a first state; and then applying a second programming pulse to at least a selected E-fuse in the plurality of E-fuses to program the selected E-fuse to a second state.

REFERENCES:
patent: 4219836 (1980-08-01), McElroy
patent: 4238839 (1980-12-01), Redfern et al.
patent: 4647340 (1987-03-01), Szluk et al.
patent: 4872140 (1989-10-01), Graham et al.
patent: 5166758 (1992-11-01), Ovshinsky et al.
patent: 6060743 (2000-05-01), Sugiyama et al.
patent: 6258700 (2001-07-01), Bohr et al.
patent: 6496416 (2002-12-01), Look
patent: 6522582 (2003-02-01), Rao et al.
patent: 6525397 (2003-02-01), Kalnitsky et al.
patent: 6597013 (2003-07-01), Romas, Jr. et al.
patent: 6671205 (2003-12-01), Look
patent: 6703680 (2004-03-01), Toyoshima
patent: 6804159 (2004-10-01), Kamiya et al.
patent: 6807079 (2004-10-01), Mei et al.
patent: 6882571 (2005-04-01), Look
patent: 6911360 (2005-06-01), Li et al.
patent: 6930920 (2005-08-01), Look
patent: 6936527 (2005-08-01), Look
patent: 7002219 (2006-02-01), de Jong et al.
patent: 7026692 (2006-04-01), Look
patent: 7068072 (2006-06-01), New et al.
patent: 7092273 (2006-08-01), Look
patent: 7098721 (2006-08-01), Ouellette et al.
patent: 7180102 (2007-02-01), Hui
patent: 2004/0100302 (2004-05-01), Pitts
patent: 2004/0124458 (2004-07-01), Kothandaraman
patent: 2006/0262161 (2006-11-01), Rice et al.
patent: 2008/0136496 (2008-06-01), He et al.
Toyoji Yamamoto et al., “Bias Temperature Instability in Scaled p+ Polysilicon Gate p-MOSFET's,” IEEE Transactions on Electron Devices, vol. 46, No. 5, May 1999, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Se-Aug Jang et al., “Effects of Thermal Processes After Silicidation on the Performance of TiSi2/Polysilicon Gate Device,” IEEE Transactions on Electron Devices, vol. 46, No. 12, Dec. 1999, pp. 2353-2356, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Rahman, Arifur et al., “Die Stacking Technology for Terabit Chip-to-Chip Communications”, Proceedings of 2006 IEEE Custom Integrated Circuits Conference (CICC), Sep. 10-13, 2006, available from IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
N. Kimizuka et al., “NBTI enchancement by nitrogen incorporation into ultrathin gat oxide for 0.10-um gate CMOS generation,” 2000 Symposium on VLSI Technology Digest of Technical Papers, Apr. 2000, pp. 92-93, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Mohsen Alavi et al., A PROM Element Based on Salicide Agglomeration of Poly Fuses in a CMOS Logic Process, Jul. 1997, pp. 855-858, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Jerome B. Lasky et al., “Comparison of Transformation to Low-Resistivity Phase and Agglomeration of TiSi2 and CoSi2,” IEEE Transactions on Electron Devices, vol. 38, No. 2, Feb. 1991, pp. 262-269, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Alexander Kalnitzky et al., CoSi2 integrated fuses on poly silicon for low voltage 0.18um CMOS applications, Sep. 1999, pp. 765-768 IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
U.S. Appl. No. 12/043,914, filed Mar. 6, 2008, Im, Hsung Jai et al., Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 12/043,091, filed Mar. 5, 2008, Im, Hsung Jai, et al., Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 12/043,099, filed Mar. 5, 2008, Im, Hsung Jai et al., Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 12/043,914, filed Mar. 6, 2008, Im, Hsung Jai et al., Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 11/973,062, filed Oct. 4, 2007, Rahman, Arifur et al., Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 11/799,886, filed May 2, 2007, Sidhu, Lakhbeer S. et al., Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 11/717,836, filed Mar. 13, 2007, Oh, Kwansuhk, et al., Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 11/588,775, filed Oct. 27, 2006, Paak, Sunhom et al., Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 11/449,171, filed Jun. 8, 2006, Ang, Boon Yong et al., Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 12/043,910, filed Mar. 6, 2008, Im, Hsung Jai et al., Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.

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