Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-10-18
2004-04-27
Kielin, Erik J. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S628000, C438S643000, C438S644000
Reexamination Certificate
active
06727177
ABSTRACT:
TECHNICAL FIELD
The invention described herein relates generally to semiconductor devices and processing. In particular, the invention relates to semiconductor devices and processes incorporating improved barrier layer structures between copper material and other layers of material. And most particularly, the invention relates improved barrier layers between copper material and low-K dielectric materials and methods of forming such devices.
BACKGROUND
The semiconductor industry has moved to using copper in various aspects of semiconductor devices due to certain advantages of copper over other metals. Copper has a first advantage of having lower resistivity than, for example, aluminum. As a result, copper circuitry suffers less from resistance-capacitance (RC) delays. This makes copper systems faster. Further, copper has increased resistance to electromigration, thereby enabling smaller scaling of semiconductor devices. However, with increased use, certain problems particular to copper have become more prevalent. One such problem is that copper has a high diffusivity through dielectric and silicon materials on which the copper is deposited. This is especially the case for so-called low-K dielectric materials, which are coming into increasingly common usage. This is problematic because the presence of copper in these materials may “poison” the materials and lead to semiconductor device failure.
In conventional methodologies, a barrier material is typically deposited on the dielectric material between the copper layer and the dielectric (or silicon) material, thereby preventing the copper from diffusing into the dielectric or silicon material. Typically, tantalum (Ta) or titanium (Ti) based barrier materials (e.g., tantalum nitrides (TaN), tantalum silicon nitrides (TaSiN), or titanium nitrides (TiN)) are used as barrier layers for copper. However, such materials also have limitations. For example, they can have porous boundaries which create a diffusion path for copper. Additionally, the thickness of existing barrier layers create some difficulties as feature size decreases. This is especially true as feature sizes decrease below 0.35 micron (:).
A conventional prior art process for creating a copper interconnect is described hereinbelow with respect to
FIGS. 1-5
. In
FIG. 1
, a typical semiconductor wafer
100
is placed in a process chamber
101
and various layers of material and circuit structures are formed thereon.
FIG. 2
is a cross-sectional view of an active device and first metal layer of a semiconductor device formed on the wafer (or substrate)
100
of FIG.
1
. In
FIG. 2
, the substrate
100
, typically silicon, has an active device
10
formed thereon. The active device
110
has a gate region
120
on the substrate
100
, and a source region
130
and a drain region
140
in the substrate
100
. The active device
110
is fabricated using conventional techniques known to one skilled in the art. A first insulating layer
150
is formed over the gate region
120
and down to the substrate
100
, over the source region
130
and drain region
140
. The first insulating layer is typically silicon dioxide; however, combinations of silicon dioxide and other doped dielectrics (e.g. BPSG, PSG) are also commonly used.
FIG. 2
shows an opening
160
which has been formed in the first insulating layer
150
and subsequently filled with a metal-containing material such as tungsten. Other material including, but not limited to, copper and aluminum may also be used. The opening
160
has been depicted as a via, but other openings including, but not limited to, trenches and inter-level interconnect structures may also be used. A metallization layer
170
is deposited over the first insulating layer
150
and the first opening
160
. The metallization layer
170
is typically copper, but may also be aluminum or tungsten. After the metallization layer
170
has been formed, material is removed to leave a metal plug
170
over the filled opening
160
. This structure is then treated to form copper interconnects.
FIG. 3
shows the topmost portion of FIG.
2
. In particular, the plug
170
is shown. An insulating layer
180
of low-K dielectric material is formed over the entire surface, including the plug
170
. Then the region over the plug
170
is etched away to define a trench
171
. Then, a barrier layer
190
is formed over the surface, including the trench
171
. Such a barrier layer
190
is typically formed of TaN or other Ta containing barrier materials or TiN barrier materials. Typically, the barrier layer
190
is formed using PVD techniques. After forming the barrier layer
190
, a copper seed layer
191
is formed over the barrier layer
190
. The seed layer provides a conductive surface for use in subsequent bulk copper deposition, which is typically performed by electroplating. With reference to
FIG. 4
, a bulk copper layer
192
(which fills in the trench
171
) is formed on copper seed layer
191
. Such bulk copper layers
192
are often formed using electroplating, but other deposition techniques are also possible, as known to those of skill in the art. Further processing, for example chemical mechanical polishing (CMP), can be used to planarize the surface, as is shown in FIG.
5
. The bulk copper layer
192
can also be sealed by the deposition of another layer of a barrier material.
For the reasons described hereinabove, as well as other reasons, an improved method of forming barrier layers for copper is needed.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, an apparatus and method for fabricating a copper interconnect having an improved copper barrier layer is disclosed.
One embodiment comprises the steps of providing a substrate having an insulating layer and an opening in the insulating layer such that an inlaid conducting structure can be formed in the opening. Further steps include forming at least one barrier layer on the insulating layer and in the opening. A copper seed layer is formed on the at least one barrier layer and a bulk layer of copper-containing material is formed on the seed layer. The substrate is then annealed.
Another embodiment comprises the steps of providing a substrate in a processing chamber, the substrate having an insulating layer and an opening in the insulating layer. Further steps include forming a first barrier layer on the insulating layer and in the opening; and forming a second barrier layer on the first barrier layer. A copper seed layer is formed on the second barrier layer and a bulk layer of copper-containing material is formed on the seed layer. The substrate is then annealed.
A further embodiment includes an insulating layer comprised of a low-K dielectric material, a first barrier layer consisting of a material selected from among tantalum and tantalum nitride, and a second barrier layer comprised of a material selected from the group consisting of palladium, chromium, magnesium, and molybdenum.
Yet another embodiment comprises a method for forming a copper barrier layer. The method includes providing a substrate in a processing chamber and forming a copper seed layer on the substrate. The seed layer is implanted with barrier materials to form an implanted seed layer and a bulk copper-containing layer is formed on the implanted seed layer. The substrate is annealed to form a final barrier layer.
In a related embodiment, the step of forming a seed layer is replaced with the steps of forming a first barrier layer on the substrate and forming a copper seed layer on the first barrier layer. After implantation of barrier material into the seed layer and bulk deposition of copper-containing material, the substrate is annealed to form a final barrier layer.
In yet another related embodiment, the step of forming a seed layer is replaced with the steps of forming a first barrier layer on the substrate and forming a second barrier layer on the first layer. A copper seed layer is formed on the second barrier layer. After implantation of barrier material into the seed layer and bulk dep
Catabay Wilbur G.
Li Ping
Wang Zhihai
Beyer Weaver & Thomas
Kielin Erik J.
LSI Logic Corporation
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