Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-05-24
2005-05-24
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S326000
Reexamination Certificate
active
06897522
ABSTRACT:
Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them.
REFERENCES:
patent: 3979582 (1976-09-01), Mims
patent: 4057788 (1977-11-01), Sage
patent: 4112507 (1978-09-01), White et al.
patent: 4173766 (1979-11-01), Hayes
patent: 4398248 (1983-08-01), Hsia et al.
patent: 4527257 (1985-07-01), Cricchi
patent: 4622656 (1986-11-01), Kamiya et al.
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 5043940 (1991-08-01), Harari
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harari
patent: 5168334 (1992-12-01), Mitchell et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5278439 (1994-01-01), Ma et al.
patent: 5311049 (1994-05-01), Tsuruta
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5315541 (1994-05-01), Harari et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5424978 (1995-06-01), Wada et al.
patent: 5426605 (1995-06-01), Van Berkel et al.
patent: 5436481 (1995-07-01), Egawa et al.
patent: 5440505 (1995-08-01), Fazio et al.
patent: 5539690 (1996-07-01), Talreja et al.
patent: 5172338 (1997-07-01), Mehrotra et al.
patent: 5661053 (1997-08-01), Yuan
patent: 5712180 (1998-01-01), Guterman et al.
patent: 5768192 (1998-06-01), Eitan
patent: 5824584 (1998-10-01), Chen et al.
patent: 5851881 (1998-12-01), Lin et al.
patent: 5887145 (1999-03-01), Harari et al.
patent: 5889303 (1999-03-01), Eckert et al.
patent: 5912844 (1999-06-01), Chen et al.
patent: 5946231 (1999-08-01), Endoh et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6030871 (2000-02-01), Eitan
patent: 6054734 (2000-04-01), Aozasa et al.
patent: 6091633 (2000-07-01), Cernea et al.
patent: 6101125 (2000-08-01), Gorman
patent: 6103573 (2000-08-01), Harari et al.
patent: 6104072 (2000-08-01), Hirota
patent: 6137718 (2000-10-01), Reisinger
patent: 6151248 (2000-11-01), Harari et al.
patent: 6177318 (2001-01-01), Ogura et al.
patent: 6181597 (2001-01-01), Nachumovsky
patent: 6201282 (2001-03-01), Eitan
patent: 6215148 (2001-04-01), Eitan
patent: 6215702 (2001-04-01), Derhacobian et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6266281 (2001-07-01), Derhacobian et al.
patent: 6281075 (2001-08-01), Yuan et al.
patent: 6313503 (2001-11-01), Lee et al.
patent: 6331952 (2001-12-01), Wang et al.
patent: 6331953 (2001-12-01), Wang et al.
patent: 6346725 (2002-02-01), Ma et al.
patent: 6349062 (2002-02-01), Thurgate
patent: 6366501 (2002-04-01), Thurgate et al.
patent: 6388293 (2002-05-01), Ogura et al.
patent: 6399441 (2002-06-01), Ogura et al.
patent: 6406960 (2002-06-01), Hopper et al.
patent: 6413821 (2002-07-01), Ebina et al.
patent: 6418062 (2002-07-01), Hayashi et al.
patent: 6436768 (2002-08-01), Yang et al.
patent: 6445030 (2002-09-01), Wu et al.
patent: 6456528 (2002-09-01), Chen
patent: 6459622 (2002-10-01), Ogura et al.
patent: 6472706 (2002-10-01), Widdershoven et al.
patent: 6477088 (2002-11-01), Ogura et al.
patent: 6487121 (2002-11-01), Thurgate et al.
patent: 6493266 (2002-12-01), Yachareni et al.
patent: 6531350 (2003-03-01), Satoh et al.
patent: 6531732 (2003-03-01), Sugita et al.
patent: 6548861 (2003-04-01), Palm et al.
patent: 6549463 (2003-04-01), Ogura et al.
patent: 6552387 (2003-04-01), Eitan
patent: 6555865 (2003-04-01), Lee et al.
patent: 6580120 (2003-06-01), Haspeslagh
patent: 6636438 (2003-10-01), Ogura et al.
patent: 6670240 (2003-12-01), Ogura et al.
patent: 6670669 (2003-12-01), Kawamura
patent: 6677200 (2004-01-01), Lee et al.
patent: 6709922 (2004-03-01), Ebina et al.
patent: 6735118 (2004-05-01), Ogura et al.
patent: 20010021126 (2001-09-01), Lavi et al.
patent: 20010055838 (2001-12-01), Walker et al.
patent: 20020064911 (2002-05-01), Eitan
patent: 20020105023 (2002-08-01), Kuo et al.
patent: 20020118574 (2002-08-01), Gongwer et al.
patent: 20020130350 (2002-09-01), Shin et al.
patent: 20020196665 (2002-12-01), Kim
patent: 20030016561 (2003-01-01), Lee et al.
patent: 20030030097 (2003-02-01), Lee et al.
patent: 20030057435 (2003-03-01), Walker
patent: 20030080372 (2003-05-01), Mikolajick
patent: 20030081456 (2003-05-01), Mikolajick
patent: 20030081460 (2003-05-01), Choi et al.
patent: 20030134476 (2003-07-01), Roizin et al.
patent: 20030209754 (2003-11-01), Haspeslagh
patent: 20040000688 (2004-01-01), Harari et al.
patent: 1 073 120 (2001-01-01), None
patent: 1 091 418 (2001-04-01), None
patent: 1 096 505 (2001-05-01), None
patent: 58-102394 (1983-06-01), None
patent: 11224940 (1999-08-01), None
patent: 960953 (1982-09-01), None
patent: WO0113378 (2001-02-01), None
patent: WO03015173 (2003-02-01), None
DiMaria, D J “Insulator Physics and Engineering : Electrically-Alterable Read-Only-Memory Applications”, Oct. 1981, Journal De Physique, C4, No. 10, Tome 42, pp. C4-1115-21.*
Aritome S et al “A Novel Side Wall Transfer-Transistor Cell (Swatt Cell) for Multi-Level Nand EEPROMs”, 1995, IEDM 95, pp 275-278.*
K. T. Chang et al., “A new SONOS memory using source-side injection for programming,”IEEE Electron Device Lett., vol. 19, 1998, pp. 253-255.
P.J. Krick, “Three-state MNOS FET memory array,”IBM Technical Disclosure Bulletin, vol. 18, No. 12, May 1976, pp. 1492-1493.
Takashi Hori et al., “A MOSFET with Si-implanted Gate-SiO,Insulator for Nonvolatile Memory Applications,”IEEE, 0-7803-0817-4/92, pp. 17.7.1-17.7.4.
D. J. DiMaria et al., “Electrically-alterable read-only-memory using Si-rich SiO, injectors and a floating polycrystalline silicon storage layer,”J. Appl. Phys., 52(7), Jul. 1981, pp. 4825-4842.
“Basic Programming Mechanisms,”Nonvolatile Semiconductor Memory Technology—A Comprehensive Guide to Understanding and Using NVSM Devices, IEEE Press series on microelectronic systems, 1998, pp. 9-25.
Kamiya, M., et al., “EPROM Cell With High Gate Injection Efficiency,”International Electronic Devices Meeting of IEEE, San Francisco, California, (Dec. 13-15, 1982) pps. 741-744.
Eitan et al., “NROM: A novel localized trapping, 2-bit nonvolatile memory cell,”IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
Nozaki, “A 1-Mb EEPROM with a MONOS memory cell for a semi-conductor disk application,”IEEE Journal of Solid State Circuits, vol. 26, No. 4, Apr. 1991, p. 498.
Chen et al., “A true single-transistor oxide-nitride-oxide EEPROM device,”IEEE Electron Device Letters, vol. EDL-8, No. 3, Mar. 1987, pp. 93-95.
Chen, Wei-Ming et al., “A Novel Flash Memory Device with SPlit Gate Source Side Injection and ONO Charge Storage Stack (SPIN)”, 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 63-64.
Roizin, Yakov, et al., “Novel Techniques for Data Retention and Leff Measurements in Two BitmicroFLASH® Memory Cells”, AIP Conference Proceedings, vol. 550, Melville, New York, 2001, pp. 181-185.
Hsia, Yukun, “Memory Applications of the MNOS”, Wescon Technical Papers, vol. 16, 1972, pp. 3303-3308.
Eitan et al., “Hot-Electron Injection into the Oxide in n-channel MOS Devices,”IEEE Transactions on Electron Devices, vol. Ed-28, No. 3, Mar. 1981, pp. 328-340.
D. Frohman-Bentchkowsky,Applied Physics Letters, vol. 18, 1971, p. 332.
D. Frohman-Bentchkowsky, “FAMOS—A new semiconductor charge storage device,”Solid-State Electron, 1974, vol. 17. p. 517.
Eitan et al., “Multilevel flash cells and their trade-offs,”IED
Guterman Daniel C.
Harari Eliyahou
Samachisa George
Yuan Jack H.
Parsons Hsue & de Runtz LLP
SanDisk Corporation
Weiss Howard
LandOfFree
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