Static information storage and retrieval – Floating gate – Multiple values
Patent
1997-07-30
1999-07-27
Phan, Trong
Static information storage and retrieval
Floating gate
Multiple values
36518524, 36518533, G11C 1604
Patent
active
059301678
ABSTRACT:
A memory system including an array of flash EEPROM cells arranged in blocks of cells that are erasable together, with individual cells storing more than one bit of data as a result of operating the individual cells with more than two detectable threshold ranges or states. Any portion of the array in which data is not stored can be used as a write cache, where individual ones of the cells store a single bit of data by operating with only two detectable threshold ranges. Data coming into the memory is initially written in available blocks in two states since writing in more than two states takes significantly more time. At a later time, in the background, the cached data is read, compressed and written back into fewer blocks of the memory in multi-state for longer term storage at a reduced cost.
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Chen Jian
Lee Douglas J.
Phan Trong
SanDisk Corporation
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