Electronic digital logic circuitry – Three or more active levels
Reexamination Certificate
2008-04-02
2010-02-02
Le, Don P (Department: 2819)
Electronic digital logic circuitry
Three or more active levels
C326S046000
Reexamination Certificate
active
07656196
ABSTRACT:
N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use one individually controlled gate. N-valued latches are provided wherein a state is represented by a signal being an independent instance of a physical phenomenon. A latch not using absence-of-signal as a state is also provided.
REFERENCES:
patent: 3129340 (1964-04-01), Baskin
patent: 3176154 (1965-03-01), Salter
patent: 3207922 (1965-09-01), Groudis et al.
patent: 3671763 (1972-06-01), Maley et al.
patent: 3671764 (1972-06-01), Maley et al.
patent: 3909634 (1975-09-01), Maley et al.
patent: 4107549 (1978-08-01), Moufah
patent: 4378595 (1983-03-01), Current
patent: 4513283 (1985-04-01), Leininger
patent: 4808854 (1989-02-01), Reinagel
patent: 5122688 (1992-06-01), Grimes
patent: 5281805 (1994-01-01), Sauer
patent: 6067180 (2000-05-01), Roberts
patent: 6133754 (2000-10-01), Olson
patent: 6191977 (2001-02-01), Lee
patent: 7263262 (2007-08-01), Covey
patent: 2002/0158663 (2002-10-01), Shemesh
patent: 2005/0194993 (2005-09-01), Lablans
Milan, Petrik “Design of Many-Valued Logical Circuits”,Czech Technical University, Prague, Czech Republic, (Feb. 8, 2004).
Ugur, Cilingiroglu et al., “Multiple-Valued Static CMOS Memory Cell”,IEEE Transactions on Circuits and Systems-II Analog and Digital Signal Processing, vol. 48, No. 3, (Mar. 2001), pp. 282-290.
Omid, Mirmotahari et al., “A Novel D-Latch In Multiple-Valued Semi-Floating-Gate Recharged Logic”,Proceedings of ISMVL '04, 4 pages.
Hanyu, et al., “A Floating-Gate-Mos-Based Multiple-Valued Associative Memory”,Proc. IEEE International Symposium on Multiple-Valued Logic, 21, (1991), pp. 24-31.
Alexey Stakhov, “Brousentsov's Ternary Principle, Bergman's Number System and Ternary Mirror-symmetrical Arithmetic”,The Computer Journal, vol. 45, No. 2, (2002), pp. 221-236.
Inaba, et al., “Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits”,IEEE, Proceedings of the 32nd International Symposium on Multiple-Valued Logic(ISMVL '02), 7 pages.
Akazawa, Masamichi et al., “Multiple-valued Inverter Using a Single-Electron-Tunneling Circuit”,IECE Trans. Electron., vol. E82-C, No. 9, (Sep. 1999), pp. 1607-1614.
Diehl Glen M.
Diehl Servilla LLC
Le Don P
Servilla Scott S.
Ternarylogic LLC
LandOfFree
Multi-state latches from n-state reversible inverters does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-state latches from n-state reversible inverters, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-state latches from n-state reversible inverters will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4196290