Multi-stage parallel data transfer

Details Multi-stage parallel data transfer Multi-stage parallel data transfer

2009-06-18

2011-10-25

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Sipo/piso

C365S220000, C365S221000

Reexamination Certificate

active

08045412

ABSTRACT:
Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.

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