Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-12-02
2001-02-13
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S687000, C438S688000, C438S685000
Reexamination Certificate
active
06187670
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to seed materials used in semiconductor processing.
BACKGROUND ART
In the process of manufacturing integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metalization”, and is performed using a number of different photolithographic and deposition techniques.
One metalization process, which is called the “damascene” technique starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and a barrier layer is deposited to coat the walls of the first channel opening to ensure good adhesion and to act as a barrier material to prevent diffusion of such conductive material into the oxide layer and the semiconductor devices (the combination of the adhesion and barrier material is collectively referred to as “barrier layer” herein). A seed layer is then deposited on the barrier layer to form a conductive material base, or “seed”, for subsequent deposition of conductive material. A conductive material is then deposited in the first channel openings and subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel oxide layer and damascenes the conductive material in the first channel openings to form the first channels.
For multiple layers of channels, another metalization process, which is called the “dual damascene” technique, is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene technique starts with the deposition of a thin stop nitride over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. A barrier layer is then deposited to coat the via openings and the second channel openings. Next, a seed layer is deposited on the barrier layer. This is followed by a deposition of the conductive material in the second channel openings and the via openings to form the second channel and the via. A second chemical-mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by a cylindrical via.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diffuses through dielectrics, such as oxide. When copper diffuses through dielectrics, it can cause damage to neighboring devices on the semiconductor substrate. To prevent diffusion, materials such as tantalum nitride (TaN), or titanium nitride (TiN) are used as barrier materials for copper. A thin adhesion layer formed of an adhesion material, such as tantalum (Ta) or titanium (Ti), is first deposited on the dielectric layer to ensure good adhesion and good electrical contact to underlying doped regions and/or conductive copper channels. A barrier layer formed of additional Ta or Ti, or TaN or TiN is used as the barrier material.
Seed layers for copper interconnect in a damascene process are traditionally deposited by sputter deposition. A problem associated with this deposition and other relatively high temperature techniques is that agglomeration often occurs over a range of temperatures from 150° C. and above, and definitely above 250° C. for “standard” seed thicknesses of above 5 nm. Agglomeration is a phenomenon in which the seed material forms low energy islands, or masses, instead of spreading out over the barrier layer. These islands cause poor sidewall step coverage and conformality, i.e., the seed layer thickness is not uniform where the agglomeration occurs. For current technology, to guarantee a minimum seed layer thickness of 5 nm anywhere in the channel or via openings as required by current technology, the seed layer is deposited to a thickness much higher than 5 nm. As the width of the channels and vias have decreased in size due to the size reduction in the semiconductor devices, an excessively thick seed layer in the wide-open areas interferes with the subsequent filling of the channel and via openings with conductive materials.
A solution, which would eliminate agglomeration during seed layer deposition and permit smooth filling of the channel or via openings by conductive materials, has long been sought, but has eluded those skilled in the art. As the semiconductor industry is moving from aluminum to copper and other type of materials which permit smaller channels and vias, it is becoming more pressing that a solution be found.
DISCLOSURE OF THE INVENTION
The present invention provides a method for forming seed layers in channel or via openings by using a two-stage approach. First, a low temperature deposition of a seed layer is performed at below the temperatures at which agglomeration occurs. This means below 250° C. for standard thicknesses, below 150° C. for other thicknesses, and preferably below 100° C. The absence of agglomeration results in a first seed layer with good adhesion and uniform thickness. Second, a deposition of the seed layer is performed at above 250° C. At the higher temperatures, the seed material has improved flow and surface mobility which results in better sidewall coverage and enhanced subsequent filling of the channel and via openings by conductive material.
The present invention further provides a method for forming a first seed layer in channel or via openings by using sputter deposition at temperatures below 100° C. to form a seed layer which is not subject to agglomeration. A subsequent deposition of a second seed layer is performed by using sputter deposition at above 250° C. to improve the seed layer sidewall step coverage and enhance the subsequent filling of the channel and via openings by conductive materials.
The present invention still further provides a two-temperature method for forming seed layers in channel or via openings with improved step coverage and conformality.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5523259 (1996-06-01), Merchant et al.
patent: 5981382 (1999-11-01), Konecni et al.
patent: 60
Brown Dirk
Iacoponi John A.
Advanced Micro Devices , Inc.
Everhart Caridad
Ishimaru Mikio
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