Multi-stage inverse toggle

Electronic digital logic circuitry – Exclusive function – With field-effect transistor

Reexamination Certificate

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C341S121000, C341S113000

Reexamination Certificate

active

11304002

ABSTRACT:
An inverse toggle circuit includes a pair of input connections for receiving each of four possible input signal combinations in a sequential rotational manner. Each of four data paths are defined to be exercised in accordance with a respective input signal combination. A first output connection is controlled by first and third data paths. A second output connection is controlled by second and fourth data paths. Each data path is defined such that a currently exercised data path generates an output signal having an asserted state on the output connection that is controlled by the currently exercised data path. The currently exercised data path is also defined to cause a next data path in the sequence to generate an output signal having a non-asserted state on the output connection that is controlled by the next data path.

REFERENCES:
patent: 5861762 (1999-01-01), Sutherland
patent: 6188263 (2001-02-01), Uenishi
patent: 6304125 (2001-10-01), Sutherland
patent: 6573758 (2003-06-01), Boerstler et al.
patent: 6987402 (2006-01-01), Lee et al.
patent: 2004/0246028 (2004-12-01), Lee et al.
Ivan E. Sutherland, “Micropipelines”, Communications of the ACM, Jun. 1989, vol. 32, No. 6.
Ivan Sutherland and Scott Fairbanks, GasP: A Minimal FIFO Control, © 2001 IEEE, no month.
Stanley Schuster, William Reohr, Peter Cook, David Heidel, Michael Immediato, Keith Jenkins, WA 17.3 Asynchronous Interlocked Pipelined CMOS Circuits Operating at 3.3-4.5GHz, 2000 IEEE International Solid-State Circuits Conference 07803-5853-8/00 © 2000 IEEE, no month.

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