Multi-stack chip size packaging method

Details Multi-stack chip size packaging method Multi-stack chip size packaging method

2008-05-20

2008-05-20

Zarneke, David A (Department: 2891)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C257SE21499, C257SE21506, C257SE21507

Reexamination Certificate

active

10747108

ABSTRACT:
In multi-stack chip size packaging a plurality chips, a first chip is electrically interconnected on a top surface of a substrate using a bump. Next, an epoxy is coated on the first chip and is stacked a second chip thereon, wherein the second chip is electrically interconnected to the substrate through an inner lead bonding. A potting solution is coated on the substrate and the second chip and installed thereon a heat spreader and then cured. An encapsulation resin is coated on a bottom surface of the substrate and electrically interconnected a third chip to the bottom surface of the substrate through a bump and an inner lead bump.

REFERENCES:
patent: 5952725 (1999-09-01), Ball
patent: 6080264 (2000-06-01), Ball
patent: 6104093 (2000-08-01), Caletka et al.
patent: 6316838 (2001-11-01), Ozawa et al.
patent: 6414384 (2002-07-01), Lo et al.
patent: 6633078 (2003-10-01), Hamaguchi et al.
patent: 6867500 (2005-03-01), Corisis et al.

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