Multi-stack-caching memory architecture

Details Multi-stack-caching memory architecture Multi-stack-caching memory architecture

1997-06-23

2000-05-23

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711120, 711170, G06F 1208

Patent

active

060676027

ABSTRACT:
The present invention provides a memory system that caches method frames using multiple stack cache management units to provide access to multiple portions of the method frames. In some embodiments of the invention, a memory system includes a main memory circuit, a first stack cache management unit, and a second stack cache management unit. The first stack cache management unit is configured to cache a first frame component of a first method frame and a second frame component of a second method frame. The second stack cache management unit is configured to cache a second frame component of the first method frame and a first frame component of the second method frame. Some embodiments of the memory system also includes a main memory cache coupled between the main memory circuit and the stack cache management units. The first frame components of the method frames can be, for example, the operand stacks method frames. The second frame components of the method frames can be, for example, the arguments and local variable areas of the method frames.

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