Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-05-08
2007-05-08
Owens, Douglas W. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257SE27060
Reexamination Certificate
active
10974145
ABSTRACT:
The drain breakdown voltage walk-in of a dual-source, dual-gate PMOS transistor is significantly reduced by utilizing source regions which have a width that is equal to or less than a width of the drain region. By utilizing source regions with widths that are equal to or less than the width of the drain region, the current density in the drain region is significantly reduced which reduces the number of hot charge carriers that are trapped at the silicon-to-silicon dioxide interface which, turn in, reduces the drain breakdown voltage walk-in rate.
REFERENCES:
patent: 5998845 (1999-12-01), Ludikhuize
patent: 2002/0072159 (2002-06-01), Nishib et al.
U.S. Appl. No. 10/974,146, filed Oct. 27, 2004, Brisbin et al.
U.S. Appl. No. 10/974,142, filed Oct. 27, 2004, Brisbin et al.
Douglas Brisbin, Andy Strachan and Prasad Chaparala, “PMOS Drain Breakdown Voltage Walk-in: A New Failure Mode in High Power BiCMOS Applications”, IEEE 2004 International Reliability Physics Symposium, Apr. 25-29, 2004, pp. 1-4 (Unnumbered).
Brisbin Douglas
Strachan Andy
Arena Andrew O.
National Semiconductor Corporation
Owens Douglas W.
Pickering Mark C.
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