Multi-slave master-slave flip-flop

Details Multi-slave master-slave flip-flop Multi-slave master-slave flip-flop

1985-10-18

1989-11-07

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Flip-flop

36518903, 365 78, 3072722, G11C 700, G11C 1900, G11C 1928

Patent

active

048796808

ABSTRACT:
A master-slave flip-flop has multiple slave cells (S1,S2,S3 . . . ) coupled to a single master cell (MASTER). The slave cell to be written to or read is accessed by select signals (WRITE and READ SELECT) coupled to the slave cells. This provides a savings in chip area of approximately the area taken up by the missing master cells which would normally correspond to the extra slave cells (S2,S3, . . . ). A Schottky transistor logic implementation can provide for a multi-port computer register file by including multiple READ SELECT signals for each master and associated set of slaves, and an output multiplexer coupled to the outputs of pairs of master-slave sets.

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