Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-03-03
2001-06-05
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S307000, C257S313000, C257S068000, C365S149000, C365S150000, C365S187000
Reexamination Certificate
active
06242772
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of integrated circuits, their operation, and manufacture. More specifically, in one embodiment the invention provides improved dynamic random access memories, methods of operating a dynamic random access memories, and methods of making a dynamic random access memories.
In the attempt to increase the number of bits on present DRAMs, elaborate processes are proposed for shrinking device dimensions, while still maintaining high enough capacitance in the storage capacitors so that data can be reliably stored, refreshed, and read. For a given bit line capacitance, parameters of primary importance in a read operation are the proportional capacitance of the storage capacitor and the voltage difference between the capacitor and the bit line. The “primary” signal in a DRAM, which is the signal on the floating bit lines before enabling the amplifier, must be larger than the deviation in the switching point between the two nodes of the amplifier.
Deviation of the switching points in the amplifier arises due to the variation in the transistor parameters of the sense amplifier. In a typical DRAM, this variation is often at least 100 mV. Other factors, such as supply variations and coupling from crossing signals may require even larger primary signals. To satisfy this requirement, a cell capacitance of 30 fF is typically required in today's DRAM devices.
While meeting with substantial success, such DRAMs have also met with certain limitations. For example, as the size of DRAMs has increased due to reductions in feature size, difficulties have been encountered in keeping the primary signal above the needed level. This has, in turn, limited the number of bits that can be placed on a bit line and, therefore, the achievable number of bits on a single DRAM substrate. Other difficulties include decreased yield and the like.
From the above it is seen that an improved dynamic random access memory is needed, along with improved methods of operating such memories and improved methods of making such memories.
SUMMARY OF THE INVENTION
An improved dynamic random access memory (DRAM) is provided by virtue of the present invention, along with an improved method of operating dynamic memory and improved method of making a dynamic memory. The DRAM according to this invention provides a large primary signal with a very small storage capacitor, often less than 10 fF. More than one transistor is included in each cell, but well established CMOS processes can be used in the manufacturing of this type of memory. According to one aspect of the invention, an improved fabrication process is utilized that further reduces effective cell size.
According to one aspect of the invention, an improved dynamic random access memory is provided. The dynamic random access memory which includes a plurality of memory cells at the intersections of word lines and bit lines, where each memory cell includes a storage capacitor for storing charge representative of a stored data value; a first, write transistor coupled to a first plate of the storage capacitor and a bit line; and a second, read transistor having a first terminal coupled to a first terminal of a third transistor and a second terminal coupled to a bit line, the third transistor comprising a gate coupled to the first plate of the storage capacitor, the word line forming a gate of both the read transistor and the write transistor. Each memory cell also has a sense node. Further, in another aspect of the invention, the dynamic random access cell includes a storage capacitor in a first semiconductor layer, transistor elements in a second semiconductor layer, above the first layer, where both first and second layers are substantially parallel with the surface of a substrate wafer. Moreover, the storage capacitor in the first layer is coupled to and placed beneath the transistor elements in the second layer.
Furthermore, a multisided capacitor for an integrated circuit, having stacked substrate layers separated by fused dielectric layers formed by a fused dielectric multilayer process is provided. The multisided capacitor includes a plurality of polysilicon gate layer plates, stacked above a gate oxide layer and above a substrate layer, and stacked below a fused dielectric layer and below a substrate layer. The plurality of polysilicon gates plates are coupled together to form one terminal of the capacitor. A plurality of plates of the capacitor in the plurality of substrate layers are placed at a fixed potential to form a second terminal of said capacitor.
In the fabrication of multilevel semiconductor integrated circuits, a method of forming a dynamic random access memory cell in multilayers of silicon semiconductor material including the steps of providing a first silicon substrate, forming a storage capacitor on the first substrate for the memory cell, and forming a first dielectric layer on a surface of the first substrate and the capacitor. Further steps include providing a second silicon substrate, forming a first silicon epitaxial layer on one surface and a second dielectric layer on a surface of the first epitaxial layer are formed on the second silicon substrate, stacking the second substrate on the first substrate, with first and second silicon dielectric layers in contact, fusing the dielectric layers together, and forming a oxide fusion interface. The next steps include removing the second substrate by etching thereby leaving the first substrate as support for first epitaxial layer, forming no fewer than one electrical component in the first epitaxial layer, and coupling the storage capacitor to the electrical component to form a dynamic random access memory cell.
An improved method of operating a dynamic random access memory is provided, which includes the steps of storing a charge representing a data value in a memory cell capacitance, activating a word line to couple the memory cell to a bit line, the charge in the memory cell either permitting or not permitting a selected current to flow to the bit line depending upon the data value, sensing a difference in voltage between two sense nodes with a sense amplifier, the voltage difference established by the selected current flow and a reference current flow to a sense node, and activating the word line to restore charge in the memory cell capacitance.
A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.
REFERENCES:
patent: 3593037 (1971-07-01), Hoff, Jr.
patent: 3706079 (1972-12-01), Vadasz et al.
patent: 3876991 (1975-04-01), Nelson et al.
patent: 4746959 (1988-05-01), Mueller
patent: 4751557 (1988-06-01), Sunami
patent: 4829018 (1989-05-01), Wahlstrom
patent: 4888631 (1989-12-01), Azuma
patent: 4896197 (1990-01-01), Mashiko
patent: 5057897 (1991-10-01), Nariani et al.
patent: 5100817 (1992-03-01), Cederbaum et al.
patent: 5112765 (1992-05-01), Cederbaum et al.
patent: 5127739 (1992-07-01), Duvvury et al.
patent: 5281548 (1994-01-01), Prall
patent: 5302542 (1994-04-01), Kishi et al.
patent: 5324980 (1994-06-01), Kusunoki
patent: 5396452 (1995-03-01), Wahlstrom
patent: 5418177 (1995-05-01), Choi
patent: 5424235 (1995-06-01), Nishihara
patent: 5438009 (1995-08-01), Yang et al.
patent: 5578849 (1996-11-01), Tadaki et al.
patent: 5612552 (1997-03-01), Owens
patent: 5650957 (1997-07-01), Choi
patent: 0175378 (1986-03-01), None
Itoh, “Trends in Megabit DRAM Circuit Design,” reprinted from IEEE JSSC, Jun. 1990, pp. 778-789, in Section 3.2: MOS Dynamic RAMS, Paper 3.8, Digital MOS Integrated Circuits II, IEEE Press, New York, NY, 1992, pp. 353-363.
Abbott et alIEEE J Sol St Civvol. 5C-8, No. 5 Oct. 1973 “A 4KMOS D.R.A.M”.
Altera Corporation
Jackson, Jr. Jerome
Townsend and Townsend / and Crew LLP
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