Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2000-07-12
2004-03-23
Phu, Phoung (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S375000, C327S159000
Reexamination Certificate
active
06711228
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a multi-rate clock generator for generating clocks in accordance with a plurality of channel data rates from reproduction data gained by A/D conversion of reproduction signals and a multi-rate digital data reproducing device for reproducing recorded digital signals at a plurality of channel rates.
BACKGROUND TECHNOLOGY
In recent years a system of reproduction by varying the number of reproduction channels and cylinder revolutions has been used quite often for the reproduction of recording tapes with different formats in a reproduction unit for digitally recorded magnetic tape.
For example, as a tape format for broadcasting tasks which digitally record video signals, there are DVCPRO and DVCPRO50, which is the high picture quality versions of DVCPRO. Those formats have exactly the same recording wave length on the tape, track pitch, track angle on the tape and number of cylinder revolutions. Total recording data rate per unit hour, however, is twice as high in DVCPRO50 as in DVCPRO.
Therefore, recording and reproducing are carried out with one channel (two heads) at 41.85 Mbps/ch in DVCPRO while recording and reproducing are carried out with two channels (four heads) at 41.715 Mbps/ch in DVCPRO50. Accordingly, data of one frame of picture signals are recorded as 10 tracks in DVCPRO while recorded as 20 tracks in DVCPRO50.
Since formats for recording tapes DVCPRO50 and recording tapes DVCPRO are different in general, video tape recorders corresponding to them, respectively, are necessary for reproducing both of them.
In addition, it is understood that since the tape format of DVCPRO50 is the same as that of DVCPRO in the track angle on the tape, the head is on track on the track of the tape of DVCPRO by cutting the tape speed in half and the revolutions in half in the video tape recorder of DVCPRO50.
Therefore, by cutting the number of cylinder revolutions and the tape speed of the video tape recorder of DVCPRO50 in half and by reproducing with two channels (four heads) at 20.8575 Mbps/ch, the DVCPRO tape can be reproduced in a convertible manner. At this time since the reproduction channel data rate is 20.8575 Mbps which is one half of 41.715 Mbps, DVCPRO50 needs a clock reproduction circuit and reproduction equalization circuit corresponding to the two channel rates.
In a prior art two types of clock reproduction circuits and reproduction equalization circuits are used by being switched in accordance with those two channel rates. An example of such a conventional magnetic tape reproduction unit is described in reference to the drawing in the following.
FIG. 9
shows a conventional multi-rate clock generator and multi-rate digital data reproducing device. In
FIG. 9
, a reproducer
1
reproduces the digitally recorded data at the first and the second channel rates.
The first rate reproduction equalizer
70
corrects the frequency characteristics of the reproduction signals reproduced at the first channel rate into desired frequency characteristics. The first rate signal discriminator
71
discriminates the output of the first rate reproduction equalizer
70
at the first sample rate so as to be decoded into the original digital data. The first rate voltage control oscillator
74
generates the clock of the basic frequency at the first channel rate, of which the frequency is variable due to the voltage. The first rate phase error detector
72
detects the phase shift between the clock generated by the first rate voltage control oscillator
74
and the reproduction signal reproduced at the first channel rate. The first rate loop filter
73
removes the high frequency component of the output of the first rate phase error detector
72
so as to control the oscillation frequency of the first rate voltage control oscillator
74
with that output.
The second rate reproduction equalizer
75
corrects the frequency characteristics of the reproduction signals reproduced at the second channel rate into the desired frequency characteristics. The second rate signal discriminator
76
discriminates the output of the second rate reproduction equalizer
75
at the second sample rate so as to be decoded into the original digital data. The second rate voltage control oscillator
79
generates the clock of the basic frequency at the second channel rate, of which the frequency is variable due to the voltage. The second rate phase error detector
77
detects a phase shift between the clock generated by the second rate voltage control oscillator
79
and the reproduction signal reproduced at the second channel rate. The second rate loop filter
78
removes the high frequency component of the output of the second rate phase error detector
77
so as to control the oscillation frequency of the second rate voltage control oscillator
79
with that output.
A reproduction data switch
80
outputs an input signal from the first rate signal discriminator
71
when reproducing at the first channel rate and outputs an input signal from the second rate signal discriminator
76
when reproducing at the second channel rate. A reproduction clock switch
81
outputs an input signal from the first rate voltage control oscillator
74
when reproducing at the first channel rate and outputs an input signal from the second rate voltage control oscillator
79
when reproducing at the second channel rate.
The conventional magnetic tape reproduction unit constructed as above generates the clock in accordance with the reproduction signal of the first channel rate by a PLL (Phase Locked Loop) circuit comprising the first rate phase error detector
72
, the first rate loop filter
73
and the first rate voltage control oscillator
74
when the reproducer
1
reproduces data at the first channel rate and decodes the recorded original digital data after the first rate reproduction equalizer
70
and the first rate signal discriminator
71
correct the frequency characteristics of the reproduction signal.
In the same way, when the reproducer
1
reproduces the data at the second channel rate the clock is generated in accordance with the reproduction signal of the second channel rate by a PLL (Phase Locked Loop) circuit comprising the second rate phase error detector
77
, the second rate loop filter
78
and the second rate voltage control oscillator
79
and the original digital data are decoded at the second channel rate after the second rate reproduction equalizer
75
and the second rate signal discriminator
76
correct the frequency characteristics of the reproduction signal.
In the above described construction, however, a plurality of voltage control oscillators, phase error detectors, loop filters and reproduction equalizers become necessary in accordance with the plurality of reproduced channel rates.
DISCLOSURE OF THE INVENTION
A purpose of the present invention is to provide a multi-rate clock generator which makes it possible to generate clocks in accordance with a plurality of reproduction channel rates by a phase error detector, a voltage control oscillator and a loop filter, of which the loop delay and the loop sensitivity are constant irrespective of the rate.
Another purpose of the present invention is to provide a multi-rate digital data reproducing device which makes it possible to decode the reproduction signal into the recorded original digital data in accordance with a plurality of reproduction channel rates by a reproduction equalizer, a phase error detector, a voltage control oscillator and a loop filter.
A multi-rate clock generator according to the first aspect of the invention is a multi-rate clock generator for generating clocks in accordance with a plurality of reproduced channel data rates, comprising: a reproduction means for reproducing the recorded digital data at a plurality of channel data rates which are n/m (n and m are positive integers) of a predetermined basic channel rate; a clock generation means for generating the first clock corresponding to the basic frequency of the basic channel rate of which the oscillation frequency is variable;
Kato Yoshikazu
Ohta Haruo
Phu Phoung
Stevens Davis Miller & Mosher LLP
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