Multi-pulse reset write scheme for phase-change memories

Details Multi-pulse reset write scheme for phase-change memories Multi-pulse reset write scheme for phase-change memories

2006-04-18

2006-04-18

Tran, Michael (Department: 2827)

Static information storage and retrieval

Systems using particular element

Resistive

C365S114000

Reexamination Certificate

active

07031181

ABSTRACT:
A memory cell device and method that includes a memory cell, and first and second write pulse signals. The memory cell has phase-change material capable of being set and capable of being reset. The first and second write pulse signals are used for a single reset operation of the memory cell. The first write pulse signal heats and melts a first portion of the phase-change material of the memory cell. The second write pulse signal heats and melts a second portion of the phase-change material of the memory cell.

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