Multi-protocol memory lookup system and method

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring

Reexamination Certificate

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Details

C711S001000, C711S108000, C711S144000, C711S173000, C711S205000, C711S217000, C711S220000, C370S254000, C370S389000, C370S392000, C370S463000, C370S466000

Reexamination Certificate

active

06826669

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to data communication networks and network content processing, and more particularly, to a memory lookup system and method that supports multiple protocols.
Data communication networks are used to interconnect many data processing resources, including computers, workstations, servers, printers, modems, and storage devices. For example, two or more computers may be connected together through a network such as a local area network, wide area network, or the Internet. Network users are able to share files, printers and other resources, send messages and run applications on remote computers. An important part of any data communication network includes the physical components or network communication devices used to interconnect the data processing resources. The design, architecture, and data processing techniques of the individual network components (e.g., routers, switches, and/or servers) may limit the speed and functionality of the data communication network. Moreover, network components are typically comprised of integrated circuit components that are configured together to carry out the operations and implement the functionality of the particular type of network component. For example, a network component such as a server may include integrated circuit components such as a microprocessor, microcontroller, application specific integrated circuit, memory, logic chips, and other types of chips. Accordingly, the design, architecture, and data processing techniques of the integrated circuit components utilized by the network components may also limit the speed and functionality of the computer network.
The speed of networking interconnect technologies is moving toward giga/tera bit per second range with the introduction and adoption of optical communication technologies. This implies an ever-increasing amount of information flowing through the Internet pipeline. Accordingly, there is an increasing demand on the network components and integrated circuit components to process and deliver the increasing volumes of information to the users. One term commonly used to describe the rate network components process information is bandwidth. Bandwidth can be affected by a variety of factors such as the efficiency of the system architecture and data processing techniques. As more data is placed on the network, the bandwidth of the network components and integrated circuit components will become a limiting factor in the speed of the overall network.
Therefore, there is a need to increase the efficiency of the network components and integrated circuit components to more efficiently use available bandwidth and improve the functionality of data networks.
SUMMARY OF THE INVENTION
Embodiments present invention include a system and method for performing memory lookup operations in a memory system. The techniques of the present invention may be used advantageously in a parser dictionary lookup unit (“DLU”) for receiving protocol string data, such as tag string data, and comparing the input protocol string data against data elements in a memory array. In one embodiment, code words corresponding to pre-loaded data elements may be transmitted on a DLU system output and used by other resources in the parser.
In one embodiment, the present invention includes a memory system comprising a memory array for storing a plurality of data elements and a plurality of code words, the memory array comprising a plurality of memory blocks, an address generator including an address line coupled to each memory block to simultaneously access individual memory locations in each memory block, the memory blocks producing a data element on a memory block output in response to receiving an address signal on the address line, and a plurality of comparators, each comparator coupled to receive a memory block output and an input signal. Furthermore, when the memory block output matches the input signal, the memory system transmits a match signal and at least one of the code words on a result bus, and when the memory block output does not match the input signal, the memory system does not transmit a match signal and at least one of the code words on the result bus.
In another embodiment, the present invention includes a memory system comprising a memory array for storing a plurality of first data fragments and second data fragments, each of the first data fragments corresponding to one of the second data fragments, a comparator unit coupled to a memory array output and to an input signal, the input signal having a first state during a first time period and a second state during a second time period, and an output stage coupled to receive a comparator unit output signal and generate a match signal when the input signal first state and second state matches one of the first data fragments and corresponding one of the second data fragments stored in the memory array. The memory array sequentially transmits at least a portion of the first data fragments to the comparator unit during the first time period for comparison with the first state of the input signal, and the memory array sequentially transmits at least a portion of the second data fragments to the comparator unit during the second time period for comparison with the second state of the input signal.
In another embodiment, the present invention includes a method comprising receiving input string data in a memory system, generating a start address, transmitting the start address to a memory array to simultaneously access a plurality of memory blocks, comparing the input string data to string data elements stored in the memory locations in each of the plurality of memory blocks identified by the start address, and transmitting a match signal and a code word when the input string data matches one of the string data elements. In another embodiment, the start address accesses one of a plurality of protocol segments in each memory block. In another embodiment, the memory array stores string data for a plurality of protocols.
In another embodiment, the present invention includes a method comprising receiving a first input string data fragment in a memory system during a first time period, comparing the first input string data fragment to first string data fragments stored in a first portion of a memory array, receiving a second input string data fragment in the memory system during a second time period, comparing the second input string data fragment to second string data fragments stored in a second portion of a memory array, and transmitting a match signal and a code word when the first and second input string data fragments matches one of the first and second string data fragments stored in the memory array. In another embodiment, the first portion of memory array comprises a plurality of memory banks, each bank storing a plurality of first string data fragments. In another embodiment, the plurality of memory banks are accessed simultaneously and first string fragments in each memory bank are compared to the first input string fragment simultaneously. In another embodiment, the memory array stores string fragments for a plurality of protocols.
In another embodiment of the present invention, the system supports a plurality of protocols including at least two protocols selected from the group consisting of HTTP, SMTP, FTP, XML, ebXML, DNS, SSL, and POP3.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings.


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Thomas et al, Nov. 4-7, 1991, IEEE MILCOM 91, vol. 1; pp. 193-197.

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