Multi-processor systems and methods for backup for...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C711S118000, C711S117000, C711S146000, C711S141000, C711S100000, C712S217000, C712S216000, C712S001000

Reexamination Certificate

active

07406565

ABSTRACT:
Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request, and a backup system that retains information associated with a previous processor execution state corresponding to an instruction associated with the speculative fill. The backup system may initiate a backup of the processor pipeline to the previous processor execution state if the speculative fill is determined to be non-coherent, and the processor pipeline may continue execution of program instructions if the speculative fill is determined to be coherent.

REFERENCES:
patent: 5197132 (1993-03-01), Steely, Jr. et al.
patent: 5222224 (1993-06-01), Flynn et al.
patent: 5404483 (1995-04-01), Stamm et al.
patent: 5420991 (1995-05-01), Konigsfeld et al.
patent: 5491811 (1996-02-01), Arimilli et al.
patent: 5519841 (1996-05-01), Sager et al.
patent: 5625829 (1997-04-01), Gephardt et al.
patent: 5651125 (1997-07-01), Witt et al.
patent: 5721855 (1998-02-01), Hinton et al.
patent: 5802577 (1998-09-01), Bhat et al.
patent: 5829040 (1998-10-01), Son
patent: 5845101 (1998-12-01), Johnson et al.
patent: 5875467 (1999-02-01), Merchant
patent: 5875472 (1999-02-01), Bauman et al.
patent: 5958019 (1999-09-01), Hagersten et al.
patent: 6032231 (2000-02-01), Gujral
patent: 6055605 (2000-04-01), Sharma et al.
patent: 6081887 (2000-06-01), Steely, Jr. et al.
patent: 6085263 (2000-07-01), Sharma et al.
patent: 6108737 (2000-08-01), Sharma et al.
patent: 6134646 (2000-10-01), Feiste et al.
patent: 6151671 (2000-11-01), D'Sa et al.
patent: 6209065 (2001-03-01), Van Doren et al.
patent: 6275905 (2001-08-01), Keller et al.
patent: 6286090 (2001-09-01), Steely, Jr. et al.
patent: 6301654 (2001-10-01), Ronchetti et al.
patent: 6317811 (2001-11-01), Deshpande et al.
patent: 6345342 (2002-02-01), Arimilli et al.
patent: 6349382 (2002-02-01), Feiste et al.
patent: 6356918 (2002-03-01), Chuang et al.
patent: 6408363 (2002-06-01), Lesartre et al.
patent: 6412067 (2002-06-01), Ramirez et al.
patent: 6457101 (2002-09-01), Bauman et al.
patent: 6493802 (2002-12-01), Razdan et al.
patent: 6535941 (2003-03-01), Kruse
patent: 6553480 (2003-04-01), Cheong et al.
patent: 6574712 (2003-06-01), Kahle et al.
patent: 6591348 (2003-07-01), Deshpande et al.
patent: 6594821 (2003-07-01), Banning et al.
patent: 6615343 (2003-09-01), Talcott et al.
patent: 6633960 (2003-10-01), Kessler et al.
patent: 6633970 (2003-10-01), Clift et al.
patent: 6651143 (2003-11-01), Mounes-Toussi
patent: 6775749 (2004-08-01), Mudgett et al.
patent: 7234029 (2007-06-01), Khare et al.
patent: 2001/0055277 (2001-12-01), Steely, Jr. et al.
patent: 2002/0009095 (2002-01-01), Van Doren et al.
patent: 2002/0099833 (2002-07-01), Steely, Jr. et al.
patent: 2002/0099913 (2002-07-01), Steely, Jr.
patent: 2002/0146022 (2002-10-01), Van Doren et al.
patent: 2002/0194290 (2002-12-01), Steely, Jr. et al.
patent: 2002/0194436 (2002-12-01), McKenney
patent: 2002/0199067 (2002-12-01), Patel et al.
patent: 2003/0069902 (2003-04-01), Narang et al.
patent: 2003/0145136 (2003-07-01), Tierney et al.
patent: 2003/0195939 (2003-10-01), Edirisooriya et al.
Vijaykumar et al. Speculative Versioning Cache. IEEE Transactions on parallel and distributed systems. vol. 12. No. 12, Dec. 2001.
M. H. Lipasti. C. B. Wilkerson. and J. P. Shen. Value locality and load value prediction. Sigplan Notices, 31(9). 1996.
T. Sato, K. Ohno, and H. Nakashima. “A Mechanism for Speculative Memory Accesses Following Synchronizing Operations,” in Proc. of Intl. Parallel and Distributed Processing Symp. IPDPS00. May 2000.
M. Cintra, J. F. Martnez, and J. Torrellas. Architectural support for scalable speculative parallelization in shared-memory multiprocessors. In Proceedings of the 27th Annual International Symposium on Computer Architecture. Jun. 2000.□□.
Rajiv Gupta. The fuzzy barrier: A mechanism for high speed synchronization of processors. In Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS III). 1989. ACM Press.
Jin Lin , Tong Chen , Wei-Chung Hsu , Pen-Chung Yew, Speculative register promotion using Advanced Load Address Table (ALAT), Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, Mar. 23-26, 2003, San Francisco, California.
Gharachorloo, et al., “Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors”, Computer Sysems Laboratory, Stanford University, CA 94305, pp. 1-14.
Gharachorloo, et al., “Architecture and Design of AlphaServer GS320”, pp. 1-16.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Multi-processor systems and methods for backup for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-processor systems and methods for backup for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-processor systems and methods for backup for... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2804255

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.