Multi-processor system verification circuitry

Details Multi-processor system verification circuitry Multi-processor system verification circuitry

2001-02-07

2008-12-23

Jaroenchonwanit, Bunjob (Department: 2152)

Electrical computers and digital processing systems: multicomput

Multicomputer data transferring via shared memory

C709S245000, C709S208000, C709S215000, C710S100000, C710S305000, C711S100000, C711S147000, C711S148000, C711S150000, C711S152000

Reexamination Certificate

active

07469273

ABSTRACT:
A multiprocessor system (40) includes a MPU subsystem (12), with master MPU (16) and shared memory (24), and a DSP/Coprocessor subsystem (14), with one or more slave DSP/Coprocessors (26). The system memory (20) is accessed by each DSP/Coprocessor subsystem (14) through a cache (28) and external memory interface (30). A verification interface (42) is used in verification mode to isolate the DSP/Coprocessor subsystem (14) from the MPU subsystem (12) and to translate system memory requests from the external memory interfaces (30) (through an arbiter (52), where multiple external memory interfaces are used) to a protocol which can be used to access the data from the shared memory (24).

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