Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-06-15
2001-01-09
Sheikh, Ayaz R. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S120000, C345S501000, C345S519000, C714S003000, C714S006130, C714S006130, C714S010000, C714S056000, C714S043000, C714S700000
Reexamination Certificate
active
06173351
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a multi-processor system in which first and second processing sets (each of which may comprise one or more processors) communicate with an I/O device bus.
The application finds particular application to fault tolerant computer systems where two or more processor sets need to communicate with an I/O device bus in lockstep with provision for identifying lockstep errors in order to detect faulty operation of the system as a whole.
In such a fault tolerant computer system, an aim is not only to be able to identify faults, but also to provide a structure which is able to provide a high degree of system availability. In order to provide high levels of system availability, it would be desirable for such systems automatically to attempt recovery from a lockstep error.
Automatic recovery from a lockstep error provides significant technical challenges in that the system has not only to detect the absence of lockstep, but also to provide an environment where the system as a whole can continue to operate.
Accordingly, an aim of the present invention is to address these technical problems.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims.
In accordance with one aspect of the invention, there is provided a bridge for a multi-processor system. The bridge comprises a first processor bus interface for connection to an I/O bus of a first processing set, a second processor bus interface for connection to an I/O bus of a second processing set and a device bus interface for connection to a device bus. It also comprises a bridge control mechanism configured to be operable to arbitrate between the first and the second processing sets for access to each others I/O bus and to the device bus in a first, split, mode, and to monitor lockstep operation of the first and second processing sets in a second, combined, mode.
By providing for operation in a split mode and in a combined mode, flexible operation is possible to cater for lockstep operation and also to provide for automatic initiation of lockstep operation and automatic recovery from lockstep errors.
It should be noted that the bus interfaces, such as the first and second processor bus interfaces and the device bus interface referenced above need not be separate components of the bridge, but may be incorporated in other components of the bridge, and may indeed be simply connections for the lines of the buses concerned.
In an embodiment of the invention, the bridge control mechanism includes an arbiter coupled to the first and second processor bus interfaces and to the device bus interface. The arbiter is operable in the split mode to arbitrate between signals on the I/O buses of the first and second processing sets for allocating access to the device bus. Thus, the bridge provides automatic arbitration for use of the buses. Indeed, the arbiter can be operable to arbitrate between signals on the I/O buses and the device bus for access to the I/O buses and the device bus.
In an embodiment of the invention, the bridge control mechanism also comprises a comparator coupled to the first and second processor bus interfaces. The comparator is operable in the combined mode to detect differences between signals on the I/O buses of the first and second processing sets as indicative of a lockstep error.
A bridge controller is coupled to an output of the comparator. The bridge controller is operable, in response to a signal indicative of a lockstep error and an output from the comparator, to cause the bridge to cease operation in the combined mode and instead to operate in a further, error mode.
Internal memory in the bridge can provide for the buffering of data, the bridge control mechanism being operable in the error mode to buffer I/O cycles pending resolution of the error.
The error mode can comprise first and second error modes.
In an initial error mode, any internal bridge write accesses initiated by the processing sets can be stored in the posted write buffer and any internal bridge read accesses initiated by the processing sets can be arbitrated. Also, in the initial error mode, any device bus write accesses initiated by the processing sets can also be stored in a posted write buffer and any device bus read accesses initiated by the processing sets can be aborted.
In a primary error mode in which a processing set asserts itself as a primary processing set, any internal bridge write accesses initiated by the primary processing set can be allowed and arbitrated, whereas any internal bridge write accesses initiated by any other processing set can be discarded. Any internal bridge read accesses initiated by the processing sets can be allowed and arbitrated. Also, any device bus write accesses initiated by the processing sets and any device bus read accesses initiated by the processing sets can be aborted.
The bridge control mechanism can be operable on power up of the bridge to operate in an initial error mode until a processor set asserts itself as a primary processing set, then be operable in the split mode to enable all processing sets to be set to a corresponding state before transferring to the combined mode.
The bridge can include a memory sub-system. It can also include a controllable routing matrix connected between the first processor bus interface, the second processor bus interface, the device bus interface and the memory sub-system. The bridge control mechanism can thus be operable to control the routing matrix selectively to interconnect the first processor bus interface, the second processor bus interface, the device bus interface and the memory sub-system according to a current mode of operation.
There can be more than two processor bus interfaces for connection to more than two I/O buses for respective processing sets.
In accordance with another aspect of the invention, there is provided a multi-processor system comprising a first processing set having an I/O bus, a second processing set having an I/O bus, a device bus and a bridge as set out above.
Each or the two or more processing sets can include at least one processor, memory and a processing set I/O bus controller.
In accordance with another aspect of the invention, there is provided a method of operating a multi-processor system as defined above, the method including selectively operating the bridge:
in a first, split, mode including arbitrating between the first and the second processing sets for access to each other and to the device bus; and
in a second, combined, mode including monitoring lockstep operation of the first and second processing sets.
REFERENCES:
patent: 4700346 (1987-10-01), Chandran
patent: 5133059 (1992-07-01), Ziegler et al.
patent: 5153881 (1992-10-01), Bruckert et al.
patent: 5226152 (1993-07-01), Klug et al.
patent: 5457779 (1995-10-01), Harrell
patent: 5500945 (1996-03-01), Maeda et al.
patent: 5533204 (1996-07-01), Tipley
patent: 5568097 (1996-10-01), Woodman, Jr.
patent: 5586253 (1996-12-01), Green et al.
patent: 5588111 (1996-12-01), Cutts, Jr. et al.
patent: 5627965 (1997-05-01), Liddell et al.
patent: 5630056 (1997-05-01), Horvath et al.
patent: 5870625 (1999-02-01), Chan et al.
patent: 5896423 (1999-04-01), Bissett et al.
patent: 5923830 (1999-07-01), Fuchs et al.
patent: 5983306 (1999-11-01), Corrigan et al.
patent: 5991866 (1999-11-01), Heller et al.
patent: 5991900 (1999-11-01), Garnett
patent: 0 752 656 (1997-01-01), None
International Search Report, Application No. PCT/US99/13086, mailed Sep. 27, 1999.
Garnett Paul J.
Oyelakin Femi A.
Rowlinson Stephen
Conley Rose & Tayon PC
Jean Frantz B.
Kivlin B. No{umlaut over ( e)}l
Sheikh Ayaz R.
Sun Microsystems Inc.
LandOfFree
Multi-processor system bridge does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-processor system bridge, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-processor system bridge will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2554693