Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Reexamination Certificate
1999-10-15
2003-11-18
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
C712S030000, C712S029000, C711S141000, C711S148000, C711S220000
Reexamination Certificate
active
06651157
ABSTRACT:
BACKGROUND OF THE INVENTION
Controlling access to memory in a multi-processor system is a difficult process, especially when many processors share data in memory. Typically, each processor maintains a small cache of most frequently used data for quick access so that time consuming requests for data to the common system memory may be avoided. However, the cache for each processor must be updated with changes made to its associated data that are reflected in the common system memory. One technique for updating processor caches is to couple each processor to what's known as a snoopy bus. A request for access to data by a requesting processor is broadcast to other processors over the snoopy bus. Each processor “snoops” into their cache to see if it has the most recent copy of the requested data. If a processor does have a most recent copy of the requested data, then that processor provides the data to the requesting processor. If no processor has a most recent copy of the requested data, a memory access is required to fulfill the requesting processor's request. If a processor updates a memory location, this update is broadcasted over the snoopy bus to the other processors in the system. Each processor checks its cache to see if it has the data corresponding to the updated memory location. If so, the processor may either remove that data and corresponding memory location from its cache or update its cache with the new information. This snoopy bus technique is effective for a small number of processors within a computer system but is ineffective for computer systems having hundreds of processors.
Another technique is to provide a directory based memory configuration. For directory based memories, a directory is used to maintain a directory entry corresponding to every entry in memory. The directory entry specifies whether the associated data in memory is valid or where the most recent copy of the data may be accessed. The directory based memory configuration avoids coupling all the processors in the computer system together and having processors be bothered handling broadcast requests found in snoopy bus designs. Communication only needs to occur with the processor having the most recent copy of the data. The size of the directory provides the constraint for this configuration as the directory would become too large to support the number of processors and memories in a large computer system. Therefore, it is desirable to provide a memory access control mechanism for computer systems with a large number of processors.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated that a need has arisen for providing a multi-processor system with processors having integrated memories and memory directories linked together through an external directory. In accordance with the present invention, a multi-processor system and method of accessing data therein are provided that substantially eliminate or reduce disadvantages and problems of conventional multi-processor systems.
According to an embodiment of the present invention, there is provided a multi-processor system that includes a plurality of processors, wherein each processor includes an integrated memory, an integrated memory controller, and an integrated memory directory. The integrated memory provides, receives, and stores data. The integrated memory controller controls access to and from the integrated memory. The integrated memory directory maintains a plurality of memory references to data within the integrated memory. The multi-processor system also includes an external switch coupled to each of the plurality of processors. The external switch passes data to and from any of the plurality of processors. The external switch includes an external directory. The external directory provides a memory reference to remote data for each of the plurality of processors that is not provided within its own integrated memory directory.
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Galles Michael B.
Kuskin Jeffrey S.
Baker & Botts L.L.P.
Silicon Graphics Inc.
Treat William M.
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