Multi processor enqueue packet circuit

Details Multi processor enqueue packet circuit Multi processor enqueue packet circuit

2007-02-06

2007-02-06

Huynh, Kim (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output command process

C710S007000, C710S052000, C712S225000

Reexamination Certificate

active

10171957

ABSTRACT:
The present invention provides a system and method for a plurality of independent processors to simultaneously assemble requests in a context memory coupled to a coprocessor. A write manager coupled to the context memory organizes segments received from multiple processors to form requests for the coprocessor. Each received segment indicates a location in the context memory, such as an indexed memory block, where the segment should be stored. Illustratively, the write manager parses the received segments to their appropriate blocks of the context memory, and detects when the last segment for a request has been received. The last segment may be identified according to a predetermined address bit, e.g. an upper order bit, that is set. When the write manager receives the last segment for a request, the write manager (1) finishes assembling the request in a block of the context memory, (2) enqueues an index associated with the memory block in an index FIFO, and (3) sets a valid bit associated with memory block. By setting the valid bit, the write manager prevents newly received segments from overwriting the assembled request that has not yet been forwarded to the coprocessor. When an index reaches the head of the index FIFO, a request is dequeued from the indexed block of the context memory and forwarded to the coprocessor.

REFERENCES:
patent: 5448708 (1995-09-01), Ward
patent: 5592625 (1997-01-01), Sandberg
patent: 6044438 (2000-03-01), Olnowich
patent: 6438678 (2002-08-01), Cashman et al.
patent: 6484224 (2002-11-01), Robins et al.
patent: 6505269 (2003-01-01), Potter
patent: 6519672 (2003-02-01), Scardamalia et al.
patent: 6529983 (2003-03-01), Marshall et al.
patent: 6564267 (2003-05-01), Lindsay
patent: 6850516 (2005-02-01), Lawson et al.
patent: 7006505 (2006-02-01), Bleszynski et al.

Affiliated with

Also associated with

Rating

Multi processor enqueue packet circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi processor enqueue packet circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi processor enqueue packet circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3831914