Multi-processor DRAM controller that prioritizes row-miss reques

Details Multi-processor DRAM controller that prioritizes row-miss reques Multi-processor DRAM controller that prioritizes row-miss reques

1996-08-05

1998-04-28

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711111, 395413, 395405, 364DIG1, G06F 1200

Patent

active

057459134

ABSTRACT:
Memory requests from multiple processors are re-ordered to maximize DRAM row hits and minimize row misses. Requests are loaded into a request queue and simultaneously decoded to determine the DRAM bank of the request. The last row address of the decoded DRAM bank is compared to the row address of the new request and a row-hit bit is set in the request queue if the row addresses match. The bank's state machine is consulted to determine if RAS is low or high, and a RAS-low bit in the request queue is set if RAS is low and the row still open. A row counter is reset for every new access but is incremented with a slow clock while the row is open but not being accessed. After a predetermined count, the row is considered "stale". A stale-row bit in the request queue is set if the decoded bank has a stale row. A request prioritizer reviews requests in the request queue and processes row-hit requests first, then row misses which are to a stale row. Lower in priority are row misses to non-stale rows which have been more recently accessed. Requests loaded into the request queue before the cache has determined if a cache hit has occurred are speculative requests and can open a new row when the old row is stale or closed.

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IBM 16 Mbit Synchronous DRAM Databook, IBM0316409C, pp. 1-100, Jan. 1996.

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