Multi-processor control device and method

Details Multi-processor control device and method Multi-processor control device and method

2008-05-16

2011-11-29

Tran, Vincent T (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S310000

Reexamination Certificate

active

08069357

ABSTRACT:
A multi-processor control device according to an example of the invention comprises a cooperative control unit which determines priorities of requests issued from processors to a shared resource which are used to suppress a total power consumption of the processors within a range in which performance constraints of programs executed by the processors are satisfied, and determines a frequency of each of the processors so as to suppress the total power consumption within the range in which the performance constraint of the each program is satisfied, a first control unit which issues requests from the processors to the shared resource in accordance with priorities determined by the cooperative control unit, and a second control unit which controls the frequency of each of the processors in accordance with the frequency determined by the cooperative control unit.

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Kondo, M., and H. Nakamura, “A Dynamic Voltage and Frequency Control Technique for a Chip Multiprocessor Architecture,” published in IPSJ [Information Processing Society of Japan] SIG [Special Interest Group] Technical Reports, vol. 2005, No. 56, May 31, 2005, 6 pages (with English abstract).
English translation of an Office Action dated Apr. 14, 2009, issued in corresponding Japanese Application No. 2007-133131.

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