Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2007-08-14
2007-08-14
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S118000
Reexamination Certificate
active
10759922
ABSTRACT:
Cache coherency rules for a multi-processor computing system that is capable of working with compressed cache lines' worth of information are described. A multi-processor computing system that is capable of working with compressed cache lines' worth of information is also described. The multi-processor computing system includes a plurality of hubs for communicating with various computing system components and for compressing/decompressing cache lines' worth of information. A processor that is capable of labeling cache lines' worth of information in accordance with the cache coherency rules is described. A processor that includes a hub as described above is also described.
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Adl-Tabatabai Ali-Reza
Ghuloum Anwar M.
Huggahalli Ram
Hum Herbert H J
Newburn Chris J.
Bataille Pierre-Michel
Blakely , Sokoloff, Taylor & Zafman LLP
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